M41T56M6F Datasheet M41T56M6F, M41T56MH6E, M41T56MH6F | P13-P15

M41T56 Clock operation

Doc ID 6104 Rev 9 13/27

3 Clock operation

The eight byte clock register (see Ta bl e 3) is used to both set the clock and to read the date

and time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are

contained within the first three registers. Bits D6 and D7 of clock register 2 (hours register)

contain the century enable bit (CEB) and the century bit (CB). Setting CEB to a '1' will cause

CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon

its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of register 3

contain the day (day of week). Registers 4, 5, and 6 contain the date (day of month), month,

and years. The final register is the control register (this is described in the clock calibration

section). Bit D7 of register 0 contains the stop bit (ST). Setting this bit to a '1' will cause the

oscillator to stop.

If the device is expected to spend a significant amount of time on the shelf, the oscillator

may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one

second.

The seven clock registers may be read one byte at a time, or in a sequential block. The

control register (address location 7) may be accessed independently. Provision has been

made to assure that a clock update does not occur while any of the seven clock addresses

are being read. If a clock address is being read, an update of the clock registers will be

delayed by 250 ms to allow the READ to be completed before the update occurs. This will

prevent a transition of data during the READ.

Note: This 250 ms delay affects only the clock register update and does not alter the actual clock

time.

Table 3. Register map

(1)

1. Keys:

S = Sign bit

FT = Frequency test bit

ST = Stop bit

OUT = Output level

X = Don't care

CEB = Century enable bit

CB = Century bit

Address

Data

Function/range

BCD format

D7 D6 D5 D4 D3 D2 D1 D0

0 ST 10 Seconds Seconds Seconds 00-59

1 X 10 Minutes Minutes Minutes 00-59

2CEB

(2)

2. When CEB is set to '1,' CB toggles from '0' to '1' or from '1' to '0' every 100 years (dependent upon the

initial value set). When CEB is set to '0,' CB does not toggle.

CB 10 hours Hours Century/hours 0-1/00-23

3XXXXX Day Day01-07

4 X X 10 date Date Date 01-31

5 X X X 10 M. Month Month 01-12

6 10 years Years Year 00-99

7 OUT FT S Calibration Control

Clock operation M41T56

14/27 Doc ID 6104 Rev 9

3.1 Clock calibration

The M41T56 is driven by a quartz-controlled oscillator with a nominal frequency of

32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator

frequency error at 25 °C, which equates to about ±1.53 minutes per month. With the

calibration bits properly set, the accuracy of each M41T56 improves to better than ±2 ppm

at 25 °C.

The oscillation rate of any crystal changes with temperature (see Figure 11 on page 15).

Most clock chips compensate for crystal frequency and temperature shift error with

cumbersome “trim” capacitors. The M41T56 design, however, employs periodic counter

correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit

at the divide by 256 stage, as shown in Figure 11 on page 15. The number of times pulses

are blanked (subtracted, negative calibration) or split (added, positive calibration) depends

upon the value loaded into the five-bit calibration byte found in the control register. Adding

counts speeds the clock up, subtracting counts slows the clock down.

The calibration byte occupies the five lower order bits (D4-D0) in the control register (addr

7). This byte can be set to represent any value between 0 and 31 in binary form. Bit D5 is

the sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration

occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have

one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is

loaded into the register, only the first 2 minutes in the 64 minutes cycle will be modified; if a

binary 6 is loaded, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator

cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of

adjustment per calibration step in the calibration register. Assuming that the oscillator is in

fact running at exactly 32,768Hz, each of the 31 increments in the calibration byte would

represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –

2.75 minutes per month.

Two methods are available for ascertaining how much calibration a given M41T56 may

require. The first involves simply setting the clock, letting it run for a month and comparing it

to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows

the designer to give the end user the ability to calibrate his clock as his environment may

require, even after the final product is packaged in a non-user serviceable enclosure. All the

designer has to do is provide a simple utility that accessed the calibration byte.

The second approach is better suited to a manufacturing environment, and involves the use

of some test equipment. When the frequency test (FT) bit, the seventh-most significant bit in

the control register, is set to a '1,' and the oscillator is running at 32,768 Hz, the FT/OUT pin

of the device will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and

direction of oscillator frequency shift at the test temperature.

For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency

error, requiring a –10(XX001010) to be loaded into the calibration byte for correction.

Note: Setting or changing the calibration byte does not affect the frequency test output frequency.

M41T56 Clock operation

Doc ID 6104 Rev 9 15/27

Figure 11. Crystal accuracy across temperature

Figure 12. Clock calibration

3.2 Output driver pin

When the FT bit is not set, the FT/OUT pin becomes an output driver that reflects the

contents of D7 of the control register. In other words, when D6 of location 7 is a '0' and D7 of

location 7 is a '0' and then the FT/OUT pin will be driven low.

Note: The FT/OUT pin is open drain which requires an external pull-up resistor.

3.3 Initial power-on defaults

Upon initial application of power to the device, the FT bit will be set to a '0' and the OUT bit

will be set to a '1.' All other register bits will initially power-on in a random state.

AI00999b

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

ΔF

= K x (T –T

)

K = –0.036 ppm/°C

± 0.006 ppm/°C

= 25°C ± 5°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27

M41T56M6F

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Real Time Clock Serial 512 (64x8)

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M41T56M6F

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