M41T56M6F Datasheet M41T56M6F, M41T56MH6E, M41T56MH6F | P7-P9

M41T56 Operation

Doc ID 6104 Rev 9 7/27

2 Operation

The M41T56 clock operates as a slave device on the serial bus. Access is obtained by

implementing a start condition followed by the correct slave address (D0h). The 64 bytes

contained in the device can then be accessed sequentially in the following order:

1. Seconds register

2. Minutes register

3. Century/hours register

4. Day register

5. Date register

6. Month register

7. Years register

8. Control register

9. RAM

The clock continually monitors V

for an out of tolerance condition. Should V

fall below

PFD

, the device terminates an access in progress and resets the device address counter.

Inputs to the device will not be recognized at this time to prevent erroneous data from being

written to the device from an out of tolerance system. When V

falls below V

BAT

, the device

automatically switches over to the battery and powers down into an ultra low current mode

of operation to conserve battery life. Upon power-up, the device switches from battery to

at V

BAT

and recognizes inputs when V

goes above V

PFD

volts.

2.1 2-wire bus characteristics

This bus is intended for communication between different ICs. It consists of two lines: one

bidirectional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the

SCL lines must be connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

● Data transfer may be initiated only when the bus is not busy.

● During data transfer, the data line must remain stable whenever the clock line is high.

● Changes in the data line while the clock line is high will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

2.1.1 Bus not busy

Both data and clock lines remain high.

2.1.2 Start data transfer

A change in the state of the data line, from high to low, while the clock is high, defines the

START condition.

Operation M41T56

8/27 Doc ID 6104 Rev 9

2.1.3 Stop data transfer

A change in the state of the data line, from low to high, while the clock is high, defines the

STOP condition.

2.1.4 Data valid

The state of the data line represents valid data when after a start condition, the data line is

stable for the duration of the high period of the clock signal. The data on the line may be

changed during the low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition.

The number of data bytes transferred between the start and stop conditions is not limited.

The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.

By definition, a device that gives out a message is called “transmitter,” the receiving device

that gets the message is called “receiver.” The device that controls the message is called

“master.” The devices that are controlled by the master are called “slaves.”

2.1.5 Acknowledge

Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low

level put on the bus by the receiver, whereas the master generates an extra acknowledge

related clock pulse.

A slave receiver which is addressed is obliged to generate an acknowledge after the

reception of each byte. Also, a master receiver must generate an acknowledge after the

reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock

pulse in such a way that the SDA line is a stable low during the high period of the

acknowledge related clock pulse. Of course, setup and hold times must be taken into

account. A master receiver must signal an end-of-data to the slave transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In this

case, the transmitter must leave the data line high to enable the master to generate the

STOP condition.

Figure 4. Serial bus data transfer sequence

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION

CHANGE OF

DATA ALLOWED

STOP

CONDITION

M41T56 Operation

Doc ID 6104 Rev 9 9/27

Figure 5. Acknowledge sequence

Figure 6. Bus timing requirements sequence

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCLK FROM

MASTER

START

CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

AI00589

SDA

tSU:STOtSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STAtBUF

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27

M41T56M6F

Mfr. #:

Buy M41T56M6F

Manufacturer:

STMicroelectronics

Description:

Real Time Clock Serial 512 (64x8)

Lifecycle:

New from this manufacturer.

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M41T56M6F

M41T56M6F

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