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PCK9448BD,151

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
9397 750 12534 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 29 November 2005 10 of 20
Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
9. Application information
9.1 Driving transmission lines
The PCK9448 clock driver was designed to drive high speed signals in a terminated
transmission line environment. To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance possible. With an output
impedance of 17 Ω (V
CC
= 3.3 V), the outputs can drive either parallel or series
terminated transmission lines.
In most high performance clock networks, point-to-point distribution of signals is the
method of choice. In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel technique terminates the signal at
the end of the line with a 50 Ω resistance to 0.5V
CC
. This technique draws a fairly high
level of DC current, and thus only a single terminated line can be driven by each output of
the PCK9448 clock driver. For the series terminated case, however, there is no DC current
draw, thus the outputs can drive multiple series terminated lines. Figure 12, illustrates an
output driving a single series terminated line versus two series terminated lines in parallel.
When taken to its extreme, the fan-out of the PCK9448 clock driver is effectively doubled
due to its capability to drive multiple lines.
Fig 12. Single versus dual transmission lines
Z
o
= 50 Ω
002aaa722
R
s
= 33 Ω
Z
o
= 50 Ω
R
s
= 33 Ω
PCK9448
OUTPUT
BUFFER
OutB1
OutB0
17 Ω
Z
o
= 50 Ω
R
s
= 33 Ω
PCK9448
OUTPUT
BUFFER
OutA
17 Ω
IN
IN
R
o
R
o
9397 750 12534 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 29 November 2005 11 of 20
Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
The waveform plots of Figure 13 show simulation results of an output driving a single line
versus two lines. In both cases the drive capability of the PCK9448 output buffer is more
than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay
measurement in the simulations a delta of only 43 ps exists between the two differently
loaded outputs. This suggests that the dual line driving need not be used exclusively to
maintain the tight output-to-output skew of the PCK9448. The output waveform in
Figure 13 shows a step in the waveform; this step is caused by the impedance mismatch
seen looking into the driver. The parallel combination of the 33 Ω series resistor plus the
output impedance does not match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5 V.
It will then increment towards the quiescent 3.0 V in steps separated by one round trip
delay (in this case 4.0 ns).
Since this step is well above the threshold region it will not cause any false clock
triggering, however designers may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving multiple lines, the situation in Figure 14
should be used. In this case the series terminating resistors are reduced such that when
the parallel combination is added to the output buffer impedance the line impedance is
perfectly matched.
Fig 13. Single versus dual line termination waveforms
V
L
V
S
Z
o
R
s
R
o
Z
o
++
------------------------------


=
Z
o
50 Ω 50 Ω
R
s
33 Ω 33 Ω
R
o
17 Ω=
||
=
||
=
V
L
3.0
25
16.5 17 25++
-----------------------------------


1.28 V==
time (ns)
0161248
002aaa679
3.0
voltage
(V)
−0.5
0
1.0
2.0
IN
OutA
t
d
= 3.8956 ns
OutB
t
d
= 3.9386 ns
9397 750 12534 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 29 November 2005 12 of 20
Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
9.2 Power consumption of the PCK9448 and thermal management
The PCK9448 dynamic electrical (AC) specification is guaranteed for the entire operating
frequency range up to 350 MHz. The PCK9448 power consumption and the associated
long-term reliability may decrease the maximum frequency limit, depending on operating
condition such as clock frequency, supply voltage, output loading, ambient temperature,
vertical convection and thermal conductivity of package and board. This section describes
the impact of these parameters on the junction temperature and gives a guideline to
estimate the PCK9448 die junction temperature and the associated device reliability. The
long-term device reliability is a function of the die temperature; refer to Table 10.
Increased power consumption will increase the die junctIon temperature and impact the
device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction
temperature of the PCK9448 needs to be controlled and the thermal impedance of the
board/package should be optimized. The power dissipated in the PCK9448 is represented
in Equation 1.
(1)
Where I
q(max)
is the static current consumption of the PCK9448, C
PD
is the power
dissipation capacitance per output, (M)ΣC
L
represents the external capacitive output load,
N is the number of active outputs (N is always 12 in the case of the PCK9448). The
PCK9448 supports driving transmission lines to maintain high signal integrity and tight
timing parameters. Any transmission line will hide the limped capacitive load at the end of
the board trace, therefore, ΣC
L
is zero for controlled transmission line systems and can be
eliminated from Equation 1. Using parallel termination output termination results in
Equation 2 for power dissipation.
Fig 14. Optimized dual line termination
Z
o
= 50 Ω
002aaa723
R
s
= 16 Ω
Z
o
= 50 Ω
R
s
= 16 Ω
PCK9448
OUTPUT
BUFFER
17 Ω
IN
Z
o
= 50 Ω
R
o
17 Ω 16 Ω 16 Ω
||
+ 50 Ω 50 Ω
||
=
25 Ω 25 Ω=
Table 10: Die junction temperature and MTBF
Junction temperature (°C) MTBF (years)
100 20.4
110 9.1
120 4.2
130 2.0
P
tot
I
q max()
V
CC
f
clk
×+ NC
PD
C
L
M
∑
+×


× V
C
C
×=
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

PCK9448BD,151

Mfr. #:
Buy PCK9448BD,151
Manufacturer:
NXP Semiconductors
Description:
IC CLK BUFFER 2:12 350MHZ 32LQFP
Lifecycle:
New from this manufacturer.
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