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PCK9448BD,151

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
9397 750 12534 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 29 November 2005 4 of 20
Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
6. Functional description
Refer to Figure 1 “Functional diagram of PCK9448”.
6.1 Function table
[1] OE = 0 will high-impedance 3-state all outputs independent of CLK_STOP.
7. Limiting values
8. Characteristics
8.1 General characteristics
[1] 200 pF capacitor discharged via a 10 Ω resistor and a 0.75 µH inductor.
[2] 100 pF capacitor discharged via a 1.5 kΩ resistor.
Table 3: Function table
Control Default Logic 0 Logic 1
CLK_SEL 1 PECL differential input selected CCLK input selected
OE 1 outputs disabled
(high-impedance state)
[1]
outputs enabled
CLK_STOP 1 outputs synchronously stopped
in logic LOW state
outputs active
Table 4: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage −0.3 +3.9 V
V
I
input voltage −0.3 V
CC
+ 0.3 V
V
O
output voltage −0.3 V
CC
+ 0.3 V
I
I
input current - ±20 mA
I
O
output current - ±50 mA
T
stg
storage temperature −65 +125 °C
Table 5: General characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
T
termination voltage
(output)
- 0.5V
CC
-V
V
esd
electrostatic discharge
voltage
Machine Model
[1]
200 - - V
Human Body Model
[2]
2000 - - V
I
latch(prot)
latch-up protection
current
200 - - mA
C
PD
power dissipation
capacitance
per output - 10 - pF
C
i
input capacitance inputs - 4.0 - pF
9397 750 12534 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 29 November 2005 5 of 20
Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
8.2 Static characteristics
[1] V
ICR
(DC) is the cross point of the differential input signal. Functional operation is obtained when the cross point is within the V
ICR
range
and the input swing lies within the V
i(p-p)
(DC) specification.
[2] The PCK9448 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of V
T
. Alternatively, the device drives up to two 50 Ω series terminated transmission lines
(V
CC
= 3.3 V) or one 50 Ω series terminated transmission line (for V
CC
= 2.5 V).
[3] Inputs have pull-down or pull-up resistors affecting the input current.
[4] I
q(max)
is the DC current consumption of the device with all outputs open and the input in its default state or open.
[1] V
ICR
(DC) is the cross point of the differential input signal. Functional operation is obtained when the cross point is within the V
ICR
range
and the input swing lies within the V
i(p-p)
(DC) specification.
[2] The PCK9448 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of V
T
. Alternatively, the device drives one 50 Ω series terminated transmission line per output
at V
CC
= 2.5 V.
[3] Inputs have pull-down or pull-up resistors affecting the input current.
[4] I
q(max)
is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 6: Static characteristics (3.3 V)
T
amb
=
−
40
°
C to +85
°
C; V
CC
= 3.3 V
±
5 %; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V
IH
HIGH-state input voltage LVCMOS 2.0 - V
CC
+ 0.3 V
V
IL
LOW-state input voltage LVCMOS −0.3 - +0.8 V
V
OH
HIGH-state output voltage I
OH
= −24 mA
[2]
2.4 - - V
V
OL
LOW-state output voltage I
OL
=24mA
[2]
- - 0.55 V
I
OL
= 12 mA - - 0.30 V
V
i(p-p)
peak-to-peak input voltage (PCLK) LVPECL 250 - - mV
V
ICR
[1]
common-mode input voltage range
(PCLK)
LVPECL 1.1 - V
CC
− 0.6 V
Z
o
output impedance - 17 - Ω
I
I
input current V
I
=V
CC
or GND
[3]
- - 300 µA
I
q(max)
maximum quiescent current all V
CC
pins
[4]
- - 2.0 mA
Table 7: Static characteristics (2.5 V)
T
amb
=
−
40
°
C to +85
°
C; V
CC
= 2.5 V
±
5 %; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V
IH
HIGH-state input voltage LVCMOS 1.7 - V
CC
+ 0.3 V
V
IL
LOW-state input voltage LVCMOS −0.3 - +0.7 V
V
OH
HIGH-state output voltage I
OH
= −15 mA
[2]
1.8 - - V
V
OL
LOW-state output voltage I
OL
= 15 mA - - 0.6 V
V
i(p-p)
peak-to-peak input voltage (PCLK) LVPECL 250 - - mV
V
ICR
[1]
common-mode input voltage range
(PCLK)
LVPECL 1.0 - V
CC
− 0.7 V
Z
o
output impedance - 19 - Ω
I
I
input current V
I
=V
CC
or GND
[3]
- - 300 µA
I
q(max)
maximum quiescent current all V
CC
pins
[4]
- - 2.0 mA
9397 750 12534 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 29 November 2005 6 of 20
Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
8.3 Dynamic characteristics
[1] Dynamic characteristics apply for parallel output termination of 50 Ω to V
T
.
[2] V
ICR
(AC) is the cross-point of the differential input signal. Normal AC operation is obtained when the cross-point is within the V
ICR
range
and the input swing lies within the V
i(p-p)
(AC) specification. Violation of V
ICR
or V
i(p-p)
impacts static phase offset.
[3] Setup and hold times are referenced to the falling edge of the selected clock signal input.
[4] Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference
input pulse width, output duty cycle, and maximum frequency specifications.
Table 8: Dynamic characteristics (3.3 V)
T
amb
=
−
40
°
C to +85
°
C; V
CC
= 3.3 V
±
5 %; unless otherwise specified.
[1]
Symbol Parameter Conditions Min Typ Max Unit
V
i(p-p)
input voltage (peak-to-peak value)
(PCLK,
PCLK)
LVPECL 400 - 1000 mV
V
ICR
[2]
common-mode input voltage range
(PCLK,
PCLK)
LVPECL 1.3 - V
CC
− 0.8 V
f
o
output frequency 0 - 350 MHz
f
i
input frequency 0 - 350 MHz
t
sk(o)
output skew time - - 150 ps
t
sk(pr)
process skew time part-to-part - - 2.0 ns
δ
o
output duty cycle f
o
< 170 MHz; δ
ref
= 50 % 45 50 55 %
t
PLH
LOW-to-HIGH propagation delay PCLK to any Q 1.6 - 3.6 ns
CCLK to any Q 1.3 - 3.3 ns
t
PHL
HIGH-to-LOW propagation delay PCLK to any Q 1.6 - 3.6 ns
CCLK to any Q 1.3 - 3.3 ns
t
PLZ
LOW to OFF-state propagation delay OE to any Q - - 11 ns
t
PHZ
HIGH to OFF-state propagation delay OE to any Q - - 11 ns
t
PZL
OFF-state to LOW propagation delay OE to any Q - - 11 ns
t
PZH
OFF-state to HIGH propagation delay OE to any Q - - 11 ns
t
su
setup time CCLK to CLK_STOP
[3]
0.0 - - ns
PCLK to
CLK_STOP
[3]
0.0 - - ns
t
h
hold time CCLK to CLK_STOP
[3]
1.0 - - ns
PCLK to
CLK_STOP
[3]
1.5 - - ns
t
r
rise time output; 0.55 V to 2.4 V 0.1 - 1.0 ns
CCLK input; 0.8 V to 2.0 V - - 1.0
[4]
ns
t
f
fall time output; 2.4 V to 0.55 V 0.1 - 1.0 ns
CCLK input; 2.0 V to 0.8 V - - 1.0
[4]
ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

PCK9448BD,151

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Buy PCK9448BD,151
Manufacturer:
NXP Semiconductors
Description:
IC CLK BUFFER 2:12 350MHZ 32LQFP
Lifecycle:
New from this manufacturer.
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