9397 750 12534 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 29 November 2005 7 of 20
Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
[1] Dynamic characteristics apply for parallel output termination of 50 to V
T
.
[2] V
ICR
(AC) is the cross-point of the differential input signal. Normal AC operation is obtained when the cross-point is within the V
ICR
range
and the input swing lies within the V
i(p-p)
(AC) specification. Violation of V
ICR
or V
i(p-p)
impacts static phase offset.
[3] See Section 9 “Application information” for part-to-part skew calculation.
[4] Setup and hold times are referenced to the falling edge of the selected clock signal input.
Table 9: Dynamic characteristics (2.5 V)
T
amb
=
40
°
C to +85
°
C; V
CC
= 2.5 V
±
5 %; unless otherwise specified.
[1]
Symbol Parameter Conditions Min Typ Max Unit
V
i(p-p)
input voltage (peak-to-peak value)
(PCLK,
PCLK)
LVPECL 400 - 1000 mV
V
ICR
[2]
common-mode input voltage range
(PCLK,
PCLK)
LVPECL 1.2 V
CC
0.8 V
f
i
input frequency 0 - 350 MHz
f
o
output frequency 0 - 350 MHz
t
sk(o)
output skew time output-to-output
[3]
- - 150 ps
t
sk(pr)
process skew time part-to-part; PCLK or
CCLK to any Q
- - 2.7 ns
δ
o
output duty cycle δ
ref
= 50 % 45 50 60 %
t
PLH
LOW-to-HIGH propagation delay PCLK to any Q 1.5 - 4.2 ns
CCLK to any Q 1.7 - 4.4 ns
t
PHL
HIGH-to-LOW propagation delay PCLK to any Q 1.5 - 4.2 ns
CCLK to any Q 1.7 - 4.4 ns
t
PLZ
LOW to OFF-state propagation delay OE to any Q - - 11 ns
t
PHZ
HIGH to OFF-state propagation delay OE to any Q - - 11 ns
t
PZL
OFF-state to LOW propagation delay OE to any Q - - 11 ns
t
PZH
OFF-state to HIGH propagation delay OE to any Q - - 11 ns
t
su
setup time CCLK to CLK_STOP
[4]
0.0 - - ns
PCLK to
CLK_STOP
[4]
0.0 - - ns
t
h
hold time CCLK to CLK_STOP
[4]
1.0 - - ns
PCLK to
CLK_STOP
[4]
1.5 - - ns
t
r
rise time input CCLK; 0.8 V to 2.0 V - - 1.0 ns
output; 0.6 V to 1.8 V 0.1 - 1.0 ns
t
f
fall time input CCLK; 2.0 V to 0.8 V - - 1.0 ns
output; 1.8 V to 0.6 V 0.1 - 1.0 ns
9397 750 12534 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 29 November 2005 8 of 20
Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
Fig 3. Output clock stop (CLK_STOP) timing diagram
CCLK
or
PCLK
CLK_STOP
Q0 to Q11
002aaa728
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs.
Fig 4. Cycle-to-cycle jitter
002aab293
t
N
t
N+1
t
jit(cc)
= | t
N
t
N+1
|
9397 750 12534 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 29 November 2005 9 of 20
Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
Fig 5. Propagation delay test reference
(PCLK/
PCLK to Qn)
Fig 6. Propagation delay test reference (CCLK to Qn)
Fig 7. Pulse skew time (t
sk(p)
) test reference
The pin-to-pin skew is defined as the worst-case
difference in propagation delay between any similar
delay path within a single device.
The time from the output controlled edge to the
non-controlled edge, divided by the time between
output controlled edges, expressed as a percentage.
Fig 8. Output skew time (t
sk(o)
) Fig 9. Output duty cycle (δ
o
)
(1) 2.4 V (V
CC
= 3.3 V)
1.8 V (V
CC
= 2.5 V)
(2) 0.55 V (V
CC
= 3.3 V)
0.6 V (V
CC
= 2.5 V)
Fig 10. Output transition time test reference Fig 11. Setup and hold time (t
su
, t
h
)
002aaa729
t
PLH
PCLK
Qn
V
ICR
V
CC
0.5V
CC
GND
PCLK
t
PHL
002aab829
t
PLH
Qn
V
CC
0.5V
CC
GND
CCLK
t
PHL
V
CC
0.5V
CC
GND
002aab290
t
PLH
CCLK
Qn
V
CC
0.5V
CC
GND
V
CC
0.5V
CC
GND
t
PHL
t
sk(p)
= | t
PLH
t
PHL
|
002aab289
t
sk(o)
V
CC
0.5V
CC
GND
V
CC
0.5V
CC
GND
t
sk(o)
002aab291
t
p
V
CC
0.5V
CC
GND
T
o
δ
o
= (t
p
÷ T
o
× 100 %)
T
o
1
f
o
-----
=
002aab292
t
f
(1)
(2)
t
r
002aaa727
t
su
CCLK
PCLK
CLK_STOP
V
CC
0.5V
CC
GND
V
CC
0.5V
CC
GND
t
h

PCK9448BD,151

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC CLK BUFFER 2:12 350MHZ 32LQFP
Lifecycle:
New from this manufacturer.
Delivery:
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