DATA SHEET
IDT8N4Q001GCD REVISION A
MARCH 6, 2012
1 ©2012 Integrated Device Technology, Inc.
Quad-Frequency Programmable XO IDT8N4Q001 REV G
General Description
The IDT8N4Q001 is a Quad-Frequency Programmable Clock
Oscillator with very flexible frequency programming capabilities. The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum high clock frequency and low phase noise performance.
The device accepts 2.5V or 3.3V supply and is packaged in a small,
lead-free (RoHS 6) 10-lead ceramic 5mm x 7mm x 1.55mm package.
Besides the four default power-up frequencies set by the FSEL0 and
FSEL1 pins, the IDT8N4Q001 can be programmed via the I
2
C
interface to output clock frequencies between 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz to a very high degree of
precision with a frequency step size of 435.9Hz ÷ N (N is the PLL
output divider). Since the FSEL0 and FSEL1 pins are mapped to four
independent PLL divider registers (P, MINT, MFRAC and N),
reprogramming those registers to other frequencies under control of
FSEL0 and FSEL1 is supported. The extended temperature range
supports wireless infrastructure, telecommunication and networking
end equipment requirements.
Features
Fourth generation FemtoClock® NG technology
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Four power-up default frequencies (see part number order
codes), re-programmable by I
2
C
I
2
C programming interface for the output clock frequency and
internal PLL control registers
Frequency programming resolution is 435.9Hz ÷N
One 2.5V, 3.3V LVDS clock output
Two control inputs for the power-up default frequency
LVCMOS/LVTTL compatible control inputs
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.253ps
(typical), integer PLL feedback configuration
RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.263ps
(typical), integer PLL feedback configuration
Full 2.5V or 3.3V supply modes
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
IDT8N4Q001
10-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
8 V
DD
7 nQ
6 Q
FSEL0 4
FSEL1 5
10 SCLK
9 SDATA
DNU 1
OE 2
GND 3
Pin Assignment
Block Diagram
Q
nQ
OSC
f
XTAL
÷MINT, MFRAC
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
I
2
C Control
Configuration Register (ROM)
(Frequency, APR, Polarity)
25
7
FSEL1
FSEL0
SCLK
SDATA
OE
Pulldown
Pulldown
Pullup
Pullup
Pullup
÷P
2
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N4Q001GCD REVISION A
MARCH 6, 2012
2 ©2012 Integrated Device Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Tables
Table 3A. OE Configuration
NOTE: OE is an asynchronous control.
Table 3B. Output Frequency Range
NOTE: Supported output frequency range. The output frequency
can be programmed to any frequency in this range and to a precision
of 218Hz or better.
Number Name Type Description
1 DNU Do not use.
2 OE Input Pullup
Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels.
3 GND Power Power supply ground.
5, 4 FSEL1, FSEL0 Input Pulldown
Default frequency select pins. See the Default Frequency Order Codes section.
LVCMOS/LVTTL interface levels.
6, 7
Q, nQ
Output Differential clock output. LVDS interface levels.
8
V
DD
Power Power supply pin.
9
SDATA
Input Pullup
I
2
C Data Input. LVCMOS/LVTTL interface levels.
10
SCLK
Input Pullup
I
2
C Clock Input. LVCMOS/LVTTL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 5.5 pF
R
PULLUP
Input Pullup Resistor 50 k
R
PULLDOWN
Input Pulldown Resistor 50 k
Input
Output EnableOE
0 Outputs Q, nQ are in high-impedance state.
1 (default) Outputs are enabled.
Output Frequency Ranges
15.476MHz to 866.67MHz
975MHz to 1,300MHz
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N4Q001GCD REVISION A
MARCH 6, 2012
3 ©2012 Integrated Device Technology, Inc.
Block Diagram with Programming Registers
Q
nQ
OSC
f
XTAL
MHz
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷ N
I
2
C Control
SCLK
SDATA
FSEL[1:0]
OE
Pullup
Pullup
Pulldown, Pulldown
Pullup
Feedback Divider M (25 Bit)
MINT
(7 bits)
MFRAC
(18 bits)
Programming Registers
P0 MINT0 MFRAC0 N0
I
2
C: 2 bits 7 bits 18 bits 7 bits
Def: 2 bits 7 bits 18 bits 7 bits
P1 MINT1 MFRAC1 N1
I
2
C: 2 bits 7 bits 18 bits 7 bits
Def: 2 bits 7 bits 18 bits 7 bits
P2 MINT2 MFRAC2 N2
I
2
C: 2 bits 7 bits 18 bits 7 bits
Def: 2 bits 7 bits 18 bits 7 bits
P3 MINT3 MFRAC3 N3
I
2
C: 2 bits 7 bits 18 bits 7 bits
Def: 2 bits 7 bits 18 bits 7 bits
Def: Power-up default register setting for I
2
C registers
00
01
10
11
34
34
34
34
34
7
27
7
30
30
30
30
18
Output Divider N
Pn, MINTn, MFRACn and Nn
34
÷P
2

8N4Q001EG-1015CDI

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Description:
Programmable Oscillators PROGRAMMABLE 5X7 OSCILLATOR
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