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LTC1272-8CCN#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
LTC1272
16
1272fc
For more information www.linear.com/1272
APPLICATIONS INFORMATION
Figure 17. ROM Mode, Two Byte Read Timing Diagram
Table 5. ROM Mode, Two Byte Read Data Bus Status
Data Outputs D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8
First Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Second Read Low Low Low Low DB11 DB10 DB9 DB8
Third Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
OLD DATA
DB7-DB0
NEW DATA
DB11-DB8
TRACK
HOLD
DATA
BUSY
RD
CS
RD
LTC1272 • F17
t
8
t
1
t
2
t
3
t
CONV
t
11
t
9
t
8
t
9
t
5
t
1
t
4
t
5
t
10
t
3
t
7
t
3
t
7
t
12
t
12
HBEN
t
7
t
4
t
1
t
8
t
9
NEW DATA
DB7-DB0
t
2
t
4
t
5
ROM Mode, Two Byte READ
As previously mentioned for a two byte read, only data
outputs D7 . . . D0/8 are used. Conversion is started in
the normal way with a Read operation and the data output
status is the same as the ROM Mode, Parallel Read. See
Figure 17 timing diagram and Table 5 data bus status.
Two more Read operations are required to access the new
conversion result. A delay equal to the LTC1272 conversion
time must be allowed between conversion start and the
second data Read operation. The second Read operation,
with HBEN high, disables conversion start and places the
high byte (4 MSBs) on data outputs D3/11 . . . DO18. A
third read operation accesses the low data byte (DB7
. . . DB0) and starts another conversion. The 4 MSB’s
appear on data outputs D11 . . . D8 during all three read
operations above.
Microprocessor Interfacing
The LTC1272 is designed to interface with microproces-
sors as a memory mapped device. The CS and RD control
inputs are common to all peripheral memory interfacing.
The HBEN input serves as a data byte select for 8-bit pro-
cessors and is normally connected to the microprocessor
address bus.
MC68000 Microprocessor
Figure 18 shows a typical interface for the MC68000. The
LTC1272 is operating in the Slow Memory Mode. Assuming
the LTC1272 is located at address C000, then the following
single 16-bit Move instruction both starts a conversion
and reads the conversion result:
Move.W $C000,D0
LTC1272
17
1272fc
For more information www.linear.com/1272
APPLICATIONS INFORMATION
At the beginning of the instruction cycle when the ADC
address is selected, BUSY and CS assert DTACK, so that
the MC68000 is forced into a Wait state. At the end of
conversion BUSY returns high and the conversion result
is placed in the D0 register of the microprocessor.
8085A, Z80 Microprocessor
Figure 19 shows a LTC1272 interface for the Z80 and
8085A. The LTC1272 is operating in the Slow Memory
Mode and a two byte read is required. Not shown in the
figure is the 8-bit latch required to demultiplex the 8085A
common address/data bus. A0 is used to assert HBEN,
so that an even address (HBEN = LOW) to the LTC1272
will start a conversion and read the low data byte. An odd
address (HBEN = HIGH) will read the high data byte. This
is accomplished with the single 16-bit Load instruction
below:
For the 8085A LHLD (B000)
For the Z80 LDHL, (B000)
This is a two byte read instruction which loads the ADC data
(address B000) into the HL register pair. During the first
read operation, BUSY forces the microprocessor to Wait
for the LTC1272 conversion. No Wait states are inserted
during the second read operation when the microprocessor
is reading the high data byte.
TMS32010 Microcomputer
Figure 20 shows an LTC1272 TMS32010 interface. The
LTC1272 is operating in the ROM Mode. The interface is
designed for a maximum TMS32010 clock frequency of
18MHz but will typically work over the full TMS32010
clock frequency range.
The LTC1272 is mapped at a port address. The following
I/O instruction starts a conversion and reads the previous
conversion result into data memory:
IN A,PA (PA = PORT ADDRESS)
When conversion is complete, a second I/O instruction
reads the up-to-date data into memory and starts another
conversion. A delay at least as long as the ADC conversion
time must be allowed between I/O instructions.
Figure 18. LTC1272 MC68000 Interface
DATA BUS
LTC1272 • F18
ADDRESS BUS
D0
D11
R/W
DTACK
AS
A1
A23
MC68000
ADDRESS
DECODE
EN
D0/8
D11
RD
BUSY
CS
HBEN
LTC1272
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. LTC1272 8085A/Z80 Interface Figure 20. LTC1272 TMS32010 Interface
DATA BUS
LTC1272 • F19
ADDRESS BUS
D0
D7
RD
WAIT
MREQ
A0
A15
Z80
8085A
ADDRESS
DECODE
EN
D0/8
D7
RD
BUSY
CS
HBEN
LINEAR CIRCUITRY OMITTED FOR CLARITY
LTC1272
A0
DATA BUS
LTC1272 • F20
PORT ADDRESS BUS
D0
D11
DEN
PA0
PA2
TMS32010
ADDRESS
DECODE
EN
D0/8
D11
RD
CS
HBEN
LTC1272
LINEAR CIRCUITRY OMITTED FOR CLARITY
LTC1272
18
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For more information www.linear.com/1272
APPLICATIONS INFORMATION
Compatibility with the AD7572
Figure 21 shows the simple, single 5V configuration
recommended for new designs with the LTC1272. If an
AD7572 replacement or upgrade is desired, the LTC1272
can be plugged into an AD7572 socket with minor modi-
fications. It can be used as a replacement or to upgrade
with sample-and-hold, single supply operation and reduced
power consumption.
The LTC1272, while consuming less power overall than the
AD7572, draws more current from the 5V supply (it draws
no power from the –15V supply). Also, a 1µs minimum
time between conversions must be provided to allow the
sample-and-hold to reacquire the analog input. Figure 22
shows that if the clock is synchronous with CS and RD,
it is only necessary to short out the 10Ω series resistor
and reverse the polarity of the 10µF bypass capacitor on
the V
REF
pin. The –15V supply is not required and can be
removed, or, because there is no internal connection to
pin 23, it can remain unmodified. The clock can be con-
sidered synchronous with CS and RD in cases where the
LTC1272 CLK IN signal is derived from the same clock as
the microprocessor reading the LTC1272.
Figure 21. Single 5V Supply, 3µs, 12-Bit Sampling ADC
10µF
IN
REF
D11 (MSB)
D10
D9
D8
D7
CLK IN
CLK OUT
HBEN
RD
CS
BUSY
NC
V
LTC1272
D6
D5
D4
DGND
D3/11
D2/10
D1/9
D0/8
A
V
AGND
DD
µP
CONTROL
LINES
0.1µF*
5V
8 OR 12-BIT
PARALLEL
BUS
ANALOG INPUT
(0V TO 5V)
10µF
0.1µF
*
FOR GROUNDING AND BYPASSING HINTS
SEE FIGURE 11 AND APPLICATION HINTS
SECTION
*
LTC1272 • 21
+
+
2.42V
V
OUTPUT
REF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

LTC1272-8CCN#PBF

Mfr. #:
Buy LTC1272-8CCN#PBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-bit 110ksps SAR ADC (8us Conversion Time)
Lifecycle:
New from this manufacturer.
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