LTC1272
8
1272fc
For more information www.linear.com/1272
APPLICATIONS INFORMATION
Conversion Details
Conversion start is controlled by the CS, RD and HBEN
inputs. At the start of conversion the successive approxi-
mation register (SAR) is reset and the three-state data
outputs are enabled. Once a conversion cycle has begun
it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the A
IN
input connects to the sample-and-hold
capacitor through a 300Ω/2.7k divider. The voltage divider
allows the LTC1272 to convert 0V to 5V input signals
while operating from a 4.5V supply. The conversion has
two phases: the sample phase and the convert phase.
During the sample phase, the comparator offset is nulled
by the feedback switch and the analog input is stored
as a charge on the sample-and-hold capacitor, C
SAMPLE
.
This phase lasts from the end of the previous conversion
until the next conversion is started. A minimum delay
between conversions (t
10
) of 1µs allows enough time
for the analog input to be acquired. During the convert
phase, the comparator feedback switch opens, putting
the comparator into the compare mode. The sample-and-
hold capacitor is switched to ground injecting the analog
input charge onto the comparator summing junction. This
input charge is successively compared to binary weighted
charges supplied by the capacitive DAC. Bit decisions are
made by the comparator (zero crossing detector) which
checks the addition of each successive weighted bit from
the DAC output. The MSB decision is made 50ns (typi-
cally) after the second falling edge of CLK IN following a
conversion start. Similarly, the succeeding bit decisions
are made approximately 50ns after a CLK IN edge until
the conversion is finished. At the end of a conversion,
the DAC output balances the A
IN
output charge. The SAR
contents (12-bit data word) which represent the A
IN
input
signal are loaded into a 12-bit latch.
Sample-and-Hold and Dynamic Performance
Traditionally A/D converters have been characterized by
such specs as offset and full-scale errors, integral nonlin-
earity and differential nonlinearity. These specs are useful
for characterizing an ADC’s DC or low frequency signal
performance.
These specs alone are not adequate to fully specify the
LTC1272 because of its high speed sampling ability. FFT
(Fast Fourrier Transform) test techniques are used to
characterize the LTC1272’s frequency response, distortion
and noise at the rated throughput.
By applying a low distortion sine wave and analyzing the
digital output using a FFT algorithm, the LTC1272’s spectral
content can be examined for frequencies outside the fun-
damental. Figure 2 shows a typical LTC1272 FFT plot.
Figure 1. A
IN
Input
V
DAC
LTC1272 • F01
+
–
C
DAC
DAC
300Ω
SAMPLE
HOLD
C
SAMPLE
2.7k
A
IN
S
A
R
12-BIT
LATCH
COMPARATOR
SAMPLE
SI
Figure 2. LTC1272 Non-Averaged, 1024 Point FFT Plot.
f
S
= 250kHz, f
IN
= 10kHz
FREQUENCY (kHz)
0
–110
AMPLITUDE (dB)
–90
–70
–50
–30
–10
0
20 40 80 120
LTC1272 • F02
–20
–40
–60
–80
–100
60 100
