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LTC1272-8CCN#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
LTC1272
4
1272fc
For more information www.linear.com/1272
DYNAMIC ACCURACY
(Note 4) f
SAMPLE
= 250kHz (LTC1272-3), 111kHz (LTC1272-8)
SYMBOL PARAMETER CONDITIONS
LTC1272-XA/C
UNITSMIN TYP MAX
S/(N+D) Signal-to-Noise Plus Distortion Ratio 10kHz Input Signal 72 dB
THD Total Harmonic Distortion (Up to 5th Harmonic) 10kHz Input Signal –82 dB
Peak Harmonic or Spurious Noise 10kHz Input Signal –82 dB
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS
LTC1272-XA/B/C
UNITSMIN TYP MAX
V
IN
Input Voltage Range 4.75V ≤ V
DD
≤ 5.25V
l
0 5 V
I
IN
Input Current
l
3.5 mA
C
IN
Input Capacitance 50 pF
t
ACQ
Sample-and-Hold Acquisition Time
l
0.45 1 µs
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 8)
SYMBOL PARAMETER CONDITIONS
LTC1272-XA/C
UNITSMIN TYP MAX
t
1
CS to RD Setup Time
l
0 ns
t
2
RD to BUSY Delay C
L
= 50pF
COM Grade
l
80 190
230
ns
ns
t
3
Data Access Time After RD↓ C
L
= 20pF
COM Grade
l
50 90
110
ns
ns
C
L
= 100pF
COM Grade
l
70 125
150
ns
ns
t
4
RD Pulse Width
COM Grade
l
t
3
t
3
ns
ns
t
5
CS to RD Hold Time
l
0 ns
t
6
Data Setup Time After BUSY
COM Grade
l
40 70
90
ns
ns
t
7
Bus Relinquish Time
COM Grade
l
20
20
30 75
85
ns
ns
t
8
HBEN to RD Setup Time
l
0 ns
t
9
HBEN to RD Hold Time
l
0 ns
t
10
Delay Between RD Operations
l
200 ns
t
11
Delay Between Conversions 1 µs
t
12
Aperture Delay of Sample and Hold Jitter <50ps 25 ns
t
13
CLK to BUSY Delay
COM Grade
l
80 170
220
ns
ns
t
CONV
Conversion Time
l
12 13 CLK
CYCLES
LTC1272
5
1272fc
For more information www.linear.com/1272
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together, unless otherwise noted.
Note 3: When the analog input voltage is taken below ground it will be
clamped by an internal diode. This product can handle, with no external
diode, input currents of greater than 60mA below ground without latch-up.
Note 4:
V
DD
= 5V, f
CLK
= 4MHz for LTC1272-3, and 1.6MHz for
LTC1272-8, t
r
= t
f
= 5ns unless otherwise specified. For best analog
performance, the LTC1272 clock should be synchronized to the RD and
CS control inputs with at least 40ns separating convert start from the
nearest clock edge.
Note 5: Linearity error is specified between the actual end points of the
A/D transfer curve.
Note 6: The LTC1272 has the same 0V to 5V input range as the AD7572
but, to achieve single supply operation, it provides a 2.42V reference
output instead of the –5.25V of the AD7572. This requires that the polarity
of the reference bypass capacitor be reversed when plugging an LTC1272
into an AD7572 socket.
Note 7: Guaranteed by design, not subject to test.
Note 8: V
DD
= 5V. Timing specifications are sample tested at 25°C to
ensure compliance. All input control signals are specified with t
r
= t
f
= 5ns
(10% to 90% of 5V) and timed from a voltage level of 1.6V. See Figures 13
through 17.
LTC1272
6
1272fc
For more information www.linear.com/1272
PIN FUNCTIONS
A
IN
(Pin 1): Analog Input, 0V to 5V Unipolar Input.
V
REF
(Pin 2): 2.42V Reference Output. When plugging into
an AD7572 socket, reverse the reference bypass capacitor
polarity and short the 10Ω series resistor.
AGND (Pin 3): Analog Ground.
D11 to D4 (Pins 4-11): Three-State Data Outputs.
DGND (Pin 12): Digital Ground.
D3/11 to D0/8 (Pins 13-16): Three-State Data Outputs.
CLK IN (Pin 17): Clock Input. An external TTL/CMOS
compatible clock may be applied to this pin or a crystal
can be connected between CLK IN and CLK OUT.
CLK OUT (Pin 18): Clock Output. An inverted CLK IN signal
appears at this pin.
HBEN (Pin 19): High Byte Enable Input. This pin is used
to multiplex the internal 12-bit conversion result into the
lower bit outputs (D7 to D0/8). See table below. HBEN
also disables conversion starts when HIGH.
RD (Pin 20): Read Input. This active low signal starts a
conversion when CS and HBEN are low. RD also enables
the output drivers when CS is low.
CS (Pin 21): The Chip Select Input must be low for the
ADC to recognize RD and HBEN inputs.
BUSY (Pin 22): The BUSY Output is low when a conver-
sion is in progress.
NC (Pin 23): Not Connected Internally. The LTC1272 does
not require negative supply. This pin can accommodate
the –15V required by the AD7572 without problems.
V
DD
(Pin 24): Positive Supply, 5V.
Data Bus Output, CS and RD = LOW
Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16
MNEMONIC* D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8
HBEN = LOW DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
HBEN = HIGH DB11 DB10 DB9 DB8 LOW LOW LOW LOW DB11 DB10 DB9 DB8
* D11...D0/8 are the ADC data output pins.
DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
0
INL ERROR (LSBs)
–1.0
1.0
512 1024 4096
LTC1272 • G01
1536 2048 2560 3072 3584
0
V
DD
= 5V
f
CLK
= 4MHz
0
0.5
–0.5
Integral Nonlinearity
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LTC1272-8CCN#PBF

Mfr. #:
Buy LTC1272-8CCN#PBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-bit 110ksps SAR ADC (8us Conversion Time)
Lifecycle:
New from this manufacturer.
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