MAX847EEI+T Datasheet MAX847EEI+, MAX847EEI+T | P10-P12

MAX847

OUT can be set as low as 1.8V; however, some run

mode functions are limited when V

OUT

is below 2.5V:

• The allowed serial-interface clock rate is reduced.

• Internal LX FET and DR1 and DR2 on-resistance

increases.

Logic Supply (REG1)

REG1 is not a regulator in the conventional sense, but

rather a 1.5Ω PFET that acts as either a switch or a volt-

age clamp, depending on the programmed OUT volt-

age. When OUT is set to 3.3V or less, REG1 operates

as a switch. When OUT is set to 3.4V or more, the

REG1 output clamps at 3.3V. This arrangement limits

REG1

to an acceptable voltage for logic when OUT is

programmed to a higher voltage (typically >4V) for

charging (see

Charger Circuit

and

Backup Linear

Regulator

sections).

Low-Noise Analog Supply (REG2)

REG2 is a linear, 24mA low-dropout regulating circuit

whose input is R2IN. The REG2 output (V

REG2

) is set by

OFS

. R

OFS

does not set an absolute voltage, but rather

an offset level from R2IN (Figure 2). V

REG2

is set by:

REG2

= V

R2IN

- 10µA · R

OFS

Typically R2IN and R

OFS

are tied to OUT, in which

case:

OUT

- V

REG2

= 10µA · R

OFS

adjusts V

OUT

- V

REG2

to allow REG2 noise rejec-

tion to be traded for voltage drop and consequent effi-

ciency loss. A 15kΩ (typical) R

OFS

value sets a 150mV

voltage difference. R2IN typically is supplied from OUT

or REG1 but can be connected elsewhere as long as the

voltage applied to R2IN does not exceed V

OUT

. For low-

est output noise on REG2, connect R2IN to REG1.

Note that the REG2 output also clamps at 3.3V.

Low-Noise, 1V Analog Supply (REG3)

REG3 is a 1V, low-noise linear regulator that supplies up

to 2mA. REG3’s input is internally connected to REG2.

PWM Frequency Synchronization

The MAX847 DC-DC converter operates with or without

a clock at the SYNC input. If a SYNC clock is used, a

PLL filter network must be connected at FILT (see R7,

C9, and C10 in Figure 2). The DC-DC converter (in

Run Mode) operates at 7f

SYNC

. The MAX847 is

designed for a 38.4kHz SYNC clock and hence a

268.8kHz switching frequency. If a SYNC clock is not

used then FILT must be tied to REF and R7, C9, and

C10 should be omitted. Note that if a SYNC clock is not

used, and FILT is

not

connected to REF, the MAX847

will not enter Run Mode.

With no SYNC clock, and FILT tied to REF, the DC-DC

converter nominally operates at 270kHz when in Run

Mode. The Run Mode switching frequency has no rela-

tion to the serial-data clock rate.

On initial power-up, the MAX847 is designed to start in

Coast Mode, with Run Mode normally commanded by

system via the serial interface, or the RUN pin, after the

system has started. Under some circumstances, the

MAX847 may power up in Run Mode. These circum-

stances are:

1) If a SYNC clock is not used (REF tied to FILT).

2) If the SYNC clock is used and is provided at initial

power-up when REG1 is 1.5V or higher.

3) If the SYNC clock is used, the connection shown in

Figure 3 is added, and the SYNC clock is present

when RSO is cleared (logic high).

These choices are outlined in Table 1.

Voltage Detectors (LBO and Reset)

The MAX847 contains two voltage-detector inputs: LBI

and RSIN. The LBI and RSIN comparator outputs are

open-drain pins (LBO and RSO) for a real-time hard-

ware output. LBO is also readable via the serial inter-

face. Both LBI and RSIN trigger at a 0.6V input

threshold and have about 18mV hysteresis. RSO also

triggers the MAX847 internal power-on reset (POR).

7-Bit ADC (CH0 Input and CH1, CH2)

Three analog channels are compared to a 7-bit, serially

programmed digital-to-analog converter (CH DAC). The

CH DAC voltage can be varied in 10mV steps from

200mV to V

REF

- 1LSB (or 1.27V) (Table 2). CH0 is an

external input, while CH1 and CH2 are signals internally

generated from the NICD and BATT pins. NICD is inter-

nally divided by four before being compared to CH

DAC, while BATT directly connects to CH2.

1-Cell, Step-Up

Two-Way Pager System IC

10 ______________________________________________________________________________________

MAX847

2N2907

OUT

FILT

RSO

Figure 3. Add PNP to allow start-up in Run Mode before the

SYNC input clock is active.

The comparison threshold voltages for each channel

are described in the following equations:

(CH0: pin 9) = D · 10mV

(CH1: NICD) = D · 40mV

(CH2: BATT) = D · 10mV

where D is the decimal equivalent of the binary code

DAC0–DAC6 (Table 2). DAC0 is the LSB. A DAC code

of 1111111 equates to D = 127. When all zeros are pro-

grammed, the CH DAC and CH_ comparators turn off.

CH0, CH1, and CH2 comparison results reside in the

three MSB locations of the output serial data (Table 5).

The CH_ OUT data is delayed by one read cycle. In

other words, each CH_ OUT bit is the result of the com-

parison made against the CH DAC voltage pro-

grammed during the previous serial-write operation.

An analog-to-digital (A/D) conversion can be performed

on a channel by using the system software to step

through a successive-approximation routine or, if the

input is partially known, by setting the CH DAC to a

voltage near the estimated point and checking succes-

sive CH_ OUT bits.

A faster A/D shortcut can be used for battery measure-

ments when the goal is a “go, no go” determination. For

this type of test, the CH DAC can simply be set to the

desired limit, and CH_ OUT supplies the result on the

next serial-write operation. One instance in which this

shortcut saves time is during a battery-impedance

check. The unloaded battery voltage can first be mea-

sured, if time allows, using one of the techniques

described in the previous paragraph. Then the magni-

tude of the loaded voltage drop can be quickly checked

with a single comparison to see if it is within the desired

limit.

The A/D circuitry can be invoked in both Run and Coast

Mode.

Open-Drain Drivers

Two open-drain drivers (DR1 and DR2) are activated

via the serial interface. DR1 and DR2 are grounded

1.8Ω (typical) NFETs that can sink up to 120mA. The

maximum sink current is limited by on-resistance and

package dissipation to about 240mA total sink current

for both switches. Note that DR1 and DR2 are designed

to sink current only from the main battery (BATT) and

cannot be pulled above BATT.

DR2 is controlled by an external input (DR2IN) as well

as a serial input bit. DR2IN is ANDed with the DR2ON

serial-control bit, allowing DR2 to drive an audio beep-

er. The audio-frequency clock is applied to DR2IN, and

ON/OFF gating is applied to DR2ON. Both DR2IN (pin

18) and DR2ON (serial bit) must be high for DR2 to

switch on. DR1 is controlled only by DR1ON (serial bit).

Run and Coast Modes

The MAX847’s default mode is Coast. Run Mode is

selected by either serial command (Table 2) or by

pulling the RUN pin high. The RUN serial bit and the

RUN pin are logically ORed. Both must be low to imple-

ment Coast Mode. In Coast Mode, the DC-DC convert-

er pulses only as needed to satisfy the load, holding

MAX847 operating current to typically 13µA. In Run

Mode the DC-DC converter employs fixed-frequency

MAX847

1-Cell, Step-Up

Two-Way Pager System IC

______________________________________________________________________________________ 11

Table 1. Run and Coast Mode Start-Up Requirements

SYNC OPERATION CIRCUIT CONNECTION START-UP MODE CAPABILITY

No SYNC clock is used.

1) Connect REF to FILT

2) Remove R7, C9, and C10

Can start in either Coast or Run Mode

by tying RUN pin appropriately. In Run

Mode the DC-DC converter operates at

270kHz.

On initial power-up, system can supply

SYNC clock to MAX847 when REG1 is

greater than 1.5V.

Use standard Figure 2 circuit

Can start in either Coast or Run Mode

by tying RUN pin appropriately. In Run

Mode the DC-DC converter operates at

SYNC

once the SYNC clock is applied.

On initial power-up, system can supply

SYNC clock to MAX847 before, or

concurrent with, RSO going high.

Add Q1 as shown in Figure 3

Can start in either Coast or Run Mode

by tying RUN pin appropriately. In Run

Mode the DC-DC converter operates at

SYNC

once the SYNC clock is applied.

On start-up, system does not supply

SYNC clock to MAX847 until after RSO

goes high.

Use standard Figure 2 circuit

Must start in Coast Mode.

Run Mode may

then be started by the system after start-up.

MAX847

pulse width modulation (PWM), as well as synchroniza-

tion, to minimize noise.

Some MAX847 functions are confined to Run Mode

while others remain active in both Run and Coast.

These are outlined as follows.

Various circuit functions can be disabled as follows:

Functions that

always remain on are:

• Serial I/O

• Reference (REF)

• OUT

• REG1

• LBI, RSIN (and LBO, RSO)

Functions that can be

programmed on or off

are (Table 1):

• DR1 and DR2

• REG2 and REG3

• NICD charger (Note: This may overload OUT if

turned on in Coast Mode when other loads are

present)

• NICD backup regulator

• CH0, CH1, CH2 and CH DAC

Functions that

always turn off in Coast Mode

are:

• SYNC and PLL circuits

• DC-DC PWM control circuits

Power-On Reset

The MAX847 has an internal POR circuit (V

OUT

< 1.6V)

to ensure an orderly power-up when a battery is first

applied. This feature is separate from the RSO com-

parator; however, if RSO goes low during operation, all

serial registers are set to the same predetermined

states as on power-up. The POR states for each regis-

ter are listed in Table 3.

Note that the MAX847 always comes out of reset in

Coast Mode; consequently, it cannot supply full power

until Run Mode is selected by either the RUN pin or ser-

ial command. System software cannot exercise full load

current until Run Mode is enabled.

Charger Circuit

A charger current source from OUT to NICD is activat-

ed via a serial bit (Table 2). The current source can

charge a small 3-cell NICD or NIMH battery (typically

coin cell) or a 1-cell lithium battery. The charge current

can be set to either 15mA or 1mA. When both 15mA

and 1mA are set, the charger runs at 15mA. OUT sets

the maximum charge (or float) voltage. When charging

is implemented, V

OUT

must also be set high enough to

allow sufficient headroom for the charger current

source. The V

OUT

- V

NICD

difference should normally

be between 0.2V and 0.5V. Charger current vs. output

voltage is graphed in the

Typical Operating

Characteristics

. Note also that charging current

reduces the OUT current available for other loads.

1-Cell, Step-Up

Two-Way Pager System IC

12 ______________________________________________________________________________________

R2 (MSB) R0 D3 D1

0 0 DR1_ON REG2_ON

0 1

LBO_Sets_

BACKUP

15mA_CHG

0 0 OV3 OV1

0 1 X X

Table 2. Serial-Bit Assignments

DR2_ON

OV4

D2 D0

RUN/

COAST

1mA_CHG

OV0

REG3_ON

BACKUP

OV2

1 DAC5 DAC3 DAC1DAC6 DAC4 DAC0DAC2

Table 3. Serial-Bit Power-On-Reset (POR) States

R2 R0 D3 D1

0 0 POR = 0 POR = 0

0 1 POR = 0 POR = 0

0 0

POR = 1

POR = 0

0 1 X X

POR = 0

D2 D0

POR = 0

POR = 1

1 POR = 0 POR = 0 POR = 0POR = 0 POR = 0 POR = 0POR = 0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

MAX847EEI+T

Mfr. #:

Buy MAX847EEI+T

Manufacturer:

Maxim Integrated

Description:

Battery Management 1 Cell Step-Up 2-Way Pager System IC

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MAX847EEI+T

MAX847EEI+T

Products related to this Datasheet