MAX847
1-Cell, Step-Up
Two-Way Pager System IC
16 ______________________________________________________________________________________
To minimize battery drain, use large values for R2 and
R4 (>100kΩ) in the above equations; 470kΩ is a good
starting value.
See the
Low-Noise Analog Supply (REG2)
section for
information on selecting R
OFS
.
Since LBO and RSO are open-drain outputs, pull-up
resistors (R5, R6) are usually required. Normally these
will be pulled up to REG1. 100kΩ is recommended as a
compromise between response time and current drain,
although other values can be used. Since LBI and RSO
are high (open circuit) during normal operation, current
normally does not flow in R5 and R6 until a low-battery
or reset event occurs.
Logic Levels
Note that since the MAX847’s internal logic is powered
from REG1, the input logic levels at the digital inputs:
DR2IN, RUN, SYNC, CS, SCL, and SDI, as well as the
logic output levels of SDO, are governed by the voltage
of REG1. Logic high inputs at these pins should not
exceed V
REG1
. Digital inputs should either be driven
from external logic (or a µP) powered from REG1, or by
open-drain logic devices that are pulled up to REG1.
Board Layout and Noise Reduction
The MAX847 makes every effort in its internal design to
minimize noise and EMI. Nevertheless, prudent layout
practices are still suggested for best performance.
Recommendations include:
1) Keep trace lengths at L1 and LX1, as well as at
PGND, as short and as wide as possible. Since LX1
swing between V
BAT
and V
OUT
at a high rate, mini-
mizing LX1 trace length serves to reduce the PC
board area that can act as an antenna.
2) The filter capacitors at OUT, REG1, REG2, and
REG3 should be placed as close as possible to
their respective pins (no more than 0.5mm away).
3) A shielded inductor at L1 will minimize radiation
noise, but may not be essential. Toroids will also
exhibit EMI performance similar to that of shielded
coils.
4) The LX1, OUT, and PGND pins are located at the
uppermost part of the IC to facilitate PC layout.
Keep power components in this area to minimize
coupling to other parts of the circuit. Other pins in
this area are digital and are not affected by close
proximity to switching nodes.
5) Use a separate short wide ground trace for PGND
and the ground side of the BATT and OUT filter
capacitors. Tie this trace to the ground plane.
Table 7. External Components
SUPPLIER PART NO. COMMENTS
CD54-220
LQH4N220K
0.94Ω, 2.6mm high,
low current, low cost
Murata
LQH3C221
0.71Ω, 2mm high, low
current, low cost
0.18Ω, 4.5mm high
Sprague 595D series
CD43-220
Tantalum
TDK NLC565050-220K
0.43Ω, 5mm high
Coilcraft DT1608C-223
0.16Ω, 3.18mm high,
shielded
AVX TPS series Tantalum
Marcon THCR series Ceramic
Sprague 595D series Tantalum
Polystor A-10300 1.5F
0.378Ω, 3.2mm high
Sumida
CDRH62B-220
0.34Ω, 3mm high,
shielded
INDUCTORS (22µH)
CAPACITORS
STORAGE CAPACITOR (optional at NICD pin)
