MAX847
1-Cell, Step-Up
Two-Way Pager System IC
_______________________________________________________________________________________ 7
______________________________________________________________Pin Description
CH0 is compared to a 7-bit DAC that adjusts from 0.2V to 1.27V. The comparison result is sent to the
CH0 OUT register.
CH09
Reset Input. Triggers RSO and resets IC when input is below 0.6V. Comparator with hysteresis (18mV).RSIN 10
Low-Battery Input. Triggers LBO and internal serial bit.LBI11
An external RC network sets the PLL loop response (at SYNC) to adjust frequency lock time versus jit-
ter: 1nF
II
(22nF + 10kΩ). Connect to REF when SYNC is not used.
FILT12
Sync Input for PWM Switch Rate. A 38.4kHz input results in a 268.8kHz PWM rate (7 times the sync
frequency).
SYNC13
Serial Clock for SPI InterfaceSCL5
Open-Drain Output for LBI ComparatorLBO 6
Reset Output. Open drain goes low when RSIN drops below 0.6V. All serial registers are reset (or set)
to POR state as well.
RSO7
1.28V Reference. Bypass with a 1µF capacitor.REF8
Power Ground. Source of LX1 NFET.PGND4
Serial Data Output for SPI InterfaceSDO3
PIN
Serial Data Input for SPI InterfaceSDI2
Connect LX1 to the inductor. LX1 is internally connected to an NFET that switches to PGND and a PFET
that switches to OUT.
LX11
FUNCTIONNAME
Resistor sets offset between OUT (or REG1 or any other point) and REG2. R
OFS
= 15kΩ results in
150mV.
OFS14
Analog GroundAGND15
Ground for DR1 and DR2 FET SourcesDRGND16
Open-Drain FET Switch. Activated via the serial-interface bit.DR117
Logic Input. ANDed with the DR2ON bit to control the DR2 switch.DR2IN18
Open-Drain FET. On via AND of the DR2ON bit and the DR2IN pin.DR219
1V, 2mA Regulator Output. On via the serial interface. Low noise.REG320
24mA REG2 Output. Linearly regulated to the voltage at the OFS pin (voltage difference =
10µA
· R
OFS
). REG2 isolates noise.
REG221
REG2 Input. Connect to OUT, REG1, or another voltage source.R2IN22
15mA or 1mA Settable Charge Current from OUT to 3-Cell NICD Stack. When the NICD_REG_ON bit is
set (Table 2), NICD becomes an input to the linear regulator at OUT, and the DC-DC converter is off.
NICD23
PFET output connected to OUT. Output is clamped such that it cannot rise above 3.3V, regardless of
the voltage set at OUT.
REG124
DC-DC Converter Output and Feedback Point. Digitally controlled from 1.8V to 4.9V in 100mV steps
(Table 6).
OUT25
Positive Connection to Battery. The IC is powered from OUT. BATT26
Chip Select for SPI Serial Interface
CS
27
Run/Coast. Permits toggling between Run and Coast Modes via logic signal. Run is selected when
either RUN or the internal RUN/COAST bit is high. Coast is selected when both are low.
RUN28
