MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
12 ______________________________________________________________________________________
5) With CS = high, wait the minimum specified time, t
CS
,
before initiating a new conversion by pulling CS low.
If a conversion is aborted by pulling CS high before
the conversion’s end, wait for the minimum acquisi-
tion time, t
ACQ
, before starting a new conversion.
CS must be held low until all data bits are clocked out.
Data can be output in two bytes or continuously, as
shown in Figure 8. The bytes contain the result of the
conversion padded with one leading 1, and trailing 0s.
SPI and MICROWIRE
When using SPI or MICROWIRE, set CPOL = 0 and
CPHA = 0. Conversion begins with a
CS
falling edge.
DOUT goes low, indicating a conversion in progress. Wait
until DOUT goes high or until the maximum specified
7.5µs conversion time elapses. Two consecutive 1-byte
reads are required to get the full 12 bits from the ADC.
DOUT output data transitions on SCLK’s falling edge and
is clocked into the µP on SCLK’s rising edge.
The first byte contains a leading 1, and seven bits of con-
version result. The second byte contains the remaining
five bits and three trailing zeros. See Figure 11 for con-
nections and Figure 12 for timing.
QSPI
Set CPOL = CPHA = 0. Unlike SPI, which requires two
1-byte reads to acquire the 12 bits of data from the ADC,
QSPI allows the minimum number of clock cycles neces-
sary to clock in the data. The MAX1240/MAX1241
requires 13 clock cycles from the µP to clock out the 12
bits of data with no trailing zeros (Figure 13). The maxi-
mum clock frequency to ensure compatibility with QSPI is
2.097MHz.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wire-
wrap boards are not recommended. Board layout should
ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital (especially
clock) lines parallel to one another, or digital lines under-
neath the ADC package.
Figure 14 shows the recommended system ground con-
nections. Establish a single-point analog ground (“star”
ground point) at GND, separate from the logic ground.
Connect all other analog grounds and DGND to this star
ground point for further noise reduction. No other digital
system ground should be connected to this single-point
analog ground. The ground return to the power supply for
this ground should be low impedance and as short as
possible for noise-free operation.
High-frequency noise in the V
DD
power supply may affect
the ADC’s high-speed comparator. Bypass this supply to
the single-point analog ground with 0.1µF and 4.7µF
bypass capacitors. Minimize capacitor lead lengths for
best supply-noise rejection. If the power supply is very
noisy, a 10Ω resistor can be connected as a lowpass filter
to attenuate supply noise (Figure 14).
