ADUM3441CRWZ-RL Datasheet ADUM3441CRWZ-RL, ADUM3440CRWZ, ADUM3442CRWZ-RL | P7-P9

Data Sheet ADuM3440/ADuM3441/ADuM3442

Rev. D | Page 7 of 24

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OR 3.3 V/5 V OPERATION

All voltages are relative to their respective ground. 5 V/3.3 V operation: 4.5 V ≤ V

DD1

≤ 5.5 V, 3.0 V ≤ V

DD2

≤ 3.6 V; 3 V/5 V operation:

3.0 V ≤ V

DD1

≤ 3.6 V, 4.5 V ≤ V

DD2

≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range,

unless otherwise noted. All typical specifications are at T

= 25°C; V

DD1

= 3.3 V, V

DD2

= 5 V or V

DD1

= 5 V, V

DD2

= 3.3 V.

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

DDI (Q)

5 V/3.3 V Operation

0.75

1.3

3.3 V/5 V Operation 0.43 0.9 mA

Output Supply Current per Channel, Quiescent I

DDO (Q)

5 V/3.3 V Operation 0.3 0.7 mA

3.3 V/5 V Operation 0.5 1.2 mA

ADuM3440, Total Supply Current, Four Channels

DC to 2 Mbps

DD1

Supply Current I

DD1 (Q)

5 V/3.3 V Operation 3 3.9 mA DC to 1 MHz logic signal frequency

3.3 V/5 V Operation 1.7 2.4 mA DC to 1 MHz logic signal frequency

DD2

Supply Current I

DD2 (Q)

5 V/3.3 V Operation 1.2 1.7 mA DC to 1 MHz logic signal frequency

3.3 V/5 V Operation 2 3 mA DC to 1 MHz logic signal frequency

150 Mbps

DD1

Supply Current I

DD1 (150)

5 V/3.3 V Operation 120 220 mA 75 MHz logic signal frequency

3.3 V/5 V Operation 63 110 mA 75 MHz logic signal frequency

DD2

Supply Current I

DD2 (150)

5 V/3.3 V Operation

75 MHz logic signal frequency

3.3 V/5 V Operation 47 55 mA 75 MHz logic signal frequency

ADuM3441, Total Supply Current, Four Channels

DC to 2 Mbps

DD1

Supply Current I

DD1 (Q)

5 V/3.3 V Operation 2.8 3.6 mA DC to 1 MHz logic signal frequency

3.3 V/5 V Operation 1.6 2.2 mA DC to 1 MHz logic signal frequency

DD2

Supply Current I

DD2 (Q)

5 V/3.3 V Operation 1.3 1.9 mA DC to 1 MHz logic signal frequency

3.3 V/5 V Operation 2.3 2.9 mA DC to 1 MHz logic signal frequency

150 Mbps

DD1

Supply Current I

DD1 (150)

5 V/3.3 V Operation

101

165

75 MHz logic signal frequency

3.3 V/5 V Operation 52 80 mA 75 MHz logic signal frequency

DD2

Supply Current I

DD2 (150)

5 V/3.3 V Operation 29 40 mA 75 MHz logic signal frequency

3.3 V/5 V Operation 65 80 mA 75 MHz logic signal frequency

ADuM3442, Total Supply Current, Four Channels

DC to 2 Mbps

DD1

Supply Current I

DD1 (Q)

5 V/3.3 V Operation 2.5 3.5 mA DC to 1 MHz logic signal frequency

3.3 V/5 V Operation 1.5 2.0 mA DC to 1 MHz logic signal frequency

DD2

Supply Current I

DD2 (Q)

5 V/3.3 V Operation 1.5 2.0 mA DC to 1 MHz logic signal frequency

3.3 V/5 V Operation 2.5 3.5 mA DC to 1 MHz logic signal frequency

ADuM3440/ADuM3441/ADuM3442 Data Sheet

Rev. D | Page 8 of 24

Parameter Symbol Min Typ Max Unit Test Conditions

150 Mbps

DD1

Supply Current I

DD1 (150)

5 V/3.3 V Operation 83 130 mA 75 MHz logic signal frequency

3.3 V/5 V Operation 40 66 mA 75 MHz logic signal frequency

DD2

Supply Current I

DD2 (150)

5 V/3.3 V Operation 40 66 mA 75 MHz logic signal frequency

3.3 V/5 V Operation 83 130 mA 75 MHz logic signal frequency

For All Models

Input Currents I

, I

−10 +0.01 +10 µA

0 ≤ V

, V

≤ V

DD1

or V

DD2

0 ≤

≤

DD1

or V

DD2

Logic High Input Threshold

, V

5 V/3.3 V Operation 2.0 V

3.3 V/5 V Operation 1.6 V

Logic Low Input Threshold

, V

5 V/3.3 V Operation 0.8 V

3.3 V/5 V Operation

0.4

Logic High Output Voltages V

OAH

, V

OBH

OCH

, V

ODH

DD1

DD2

) − 0.1

DD1

DD2

)

V I

= −20 µA, V

= V

IxH

DD1

DD2

) − 0.4

DD1

DD2

) − 0.2

V I

= −4 mA, V

= V

IxH

Logic Low Output Voltages

OAL

, V

OBL

OCL

, V

ODL

0.0

0.1

= 20 µA, V

= V

IxL

0.04 0.1 V I

= 400 µA, V

= V

IxL

0.2 0.4 V I

= 4 mA, V

= V

IxL

SWITCHING SPECIFICATIONS

Minimum Pulse Width

PW 6.67 ns C

= 15 pF, CMOS signal levels

Maximum Data Rate

150 Mbps C

= 15 pF, CMOS signal levels

Propagation Delay

PHL

, t

PLH

20 35 ns C

= 15 pF, CMOS signal levels

Pulse Width Distortion, |t

PLH

− t

PHL

PWD

0.5 2 ns C

= 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C C

= 15 pF, CMOS signal levels

Propagation Delay Skew

PSK

15 ns C

= 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels

PSKCD

2 ns C

= 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Opposing Directional Channels

PSKOD

5 ns C

= 15 pF, CMOS signal levels

For All Models

Output Disable Propagation Delay

(High/Low to High Impedance)

PHZ

, t

PLH

6 8 ns C

= 15 pF, CMOS signal levels

Output Enable Propagation Delay

(High Impedance to High/Low)

PZH

, t

PZL

6 8 ns C

= 15 pF, CMOS signal levels

Output Rise/Fall Time (10% to 90%)

= 15 pF, CMOS signal levels

5 V/3 V Operation 3.0 ns

3 V/5 V Operation 2.5 ns

Common-Mode Transient Immunity

at Logic High Output

|CM

| 25 35 kV/µs V

= V

DD1

or V

DD2

, V

= 1000 V,

transient magnitude = 800 V

Common-Mode Transient Immunity

at Logic Low Output

|CM

kV/µs

= 0 V, V

= 1000 V,

transient magnitude = 800 V

Refresh Rate f

5 V/3.3 V Operation 1.2 Mbps

3.3 V/5 V Operation

1.1

Mbps

Input Dynamic Supply Current per Channel

DDI (D)

5 V/3.3 V Operation 0.196 mA/Mbps

3.3 V/5 V Operation 0.076 mA/Mbps

Output Dynamic Supply Current per Channel

DDO (D)

5 V/3.3 V Operation 0.028 mA/Mbps

3.3 V/5 V Operation 0.01 mA/Mbps

Data Sheet ADuM3440/ADuM3441/ADuM3442

Rev. D | Page 9 of 24

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.

See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through

Figure 15 for total V

DD1

and V

DD2

supply currents as a function of data rate for ADuM3440/ADuM3441/ADuM3442 channel configurations.

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

PHL

propagation delay is measured from the 50% level of the falling edge of the V

signal to the 50% level of the falling edge of the V

signal. t

PLH

propagation delay is

measured from the 50% level of the rising edge of the V

signal to the 50% level of the rising edge of the V

signal.

PSK

is the magnitude of the worst-case difference in t

PHL

or t

PLH

that is measured between units at the same operating temperature, supply voltages, and output load

within the recommended operating conditions.

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with

inputs on opposing sides of the isolation barrier.

is the maximum common-mode voltage slew rate that can be sustained while maintaining V

> 0.8 V

DDO

. CM

is the maximum common-mode voltage slew rate

that can be sustained while maintaining V

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

magnitude is the range over which the common mode is slewed.

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current

for a given data rate.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

ADUM3441CRWZ-RL

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Digital Isolators Quad-CH High Speed Digital

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