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CY7C15632KV18-450BZXC

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CY7C15632KV18
Document Number: 001-54932 Rev. *K Page 19 of 30
Power Up Sequence in QDR II+ SRAM
QDR II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power Up Sequence
■ Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐ Apply V
DD
before V
DDQ
.
❐ Apply V
DDQ
before V
REF
or at the same time as V
REF
.
❐ Drive DOFF HIGH.
■ Provide stable DOFF (HIGH), power and clock (K, K) for 20 s
to lock the PLL.
PLL Constraints
■ PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
KC Var
.
■ The PLL functions at frequencies down to 120 MHz.
■ If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 s of stable clock to
relock to the desired clock frequency.
Figure 4. Power Up Waveforms
> 20μs Stable clock
Start Normal
Operation
DOFF
Stable (< +/- 0.1V DC per 50ns )
Fix HIGH (or tie to V
DDQ
)
K
K
DDQDD
V
V
/
DDQDD
V
V
/
Clock Start
(Clock Starts after Stable)
DDQ
DD
V
V
/
~
~
~
Unstable Clock
CY7C15632KV18
Document Number: 001-54932 Rev. *K Page 20 of 30
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature
with Power Applied .................................. –55 °C to +125 °C
Supply Voltage on V
DD
Relative to GND .....–0.5 V to +2.9 V
Supply Voltage on V
DDQ
Relative to GND .... –0.5 V to +V
DD
DC Applied to Outputs in High Z ......–0.5 V to V
DDQ
+ 0.3 V
DC Input Voltage
[20]
...........................–0.5 V to V
DD
+ 0.3 V
Current into Outputs (LOW) ........................................20 mA
Static Discharge Voltage
(MIL-STD-883, M. 3015) .........................................> 2001 V
Latch up Current ....................................................> 200 mA
Operating Range
Range
Ambient
Temperature (T
A
)
V
DD
[21]
V
DDQ
[21]
Commercial 0 °C to +70 °C 1.8 ± 0.1 V 1.4 V to V
DD
Industrial –40 °C to +85 °C
Neutron Soft Error Immunity
Parameter Description
Test
Conditions
Typ Max* Unit
LSBU Logical
Single-Bit
Upsets
25 °C 197 216 FIT/M
b
LMBU Logical
Multi-Bit
Upsets
25 °C 0 0.01 FIT/M
b
SEL Single Event
Latch up
85 °C 0 0.1 FIT/D
ev
* No LMBU or SEL events occurred during testing; this column represents a
statistical
2
, 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter
[22]
Description Test Conditions Min Typ Max Unit
V
DD
Power Supply Voltage 1.7 1.8 1.9 V
V
DDQ
I/O Supply Voltage 1.4 1.5 V
DD
V
V
OH
Output HIGH Voltage Note 23 V
DDQ
/2 – 0.12 – V
DDQ
/2 + 0.12 V
V
OL
Output LOW Voltage Note 24 V
DDQ
/2 – 0.12 – V
DDQ
/2 + 0.12 V
V
OH(LOW)
Output HIGH Voltage I
OH
=0.1 mA, Nominal Impedance V
DDQ
– 0.2 – V
DDQ
V
V
OL(LOW)
Output LOW Voltage I
OL
= 0.1 mA, Nominal Impedance V
SS
–0.2V
V
IH
Input HIGH Voltage V
REF
+ 0.1 – V
DDQ
+ 0.15 V
V
IL
Input LOW Voltage –0.15 – V
REF
– 0.1 V
I
X
Input Leakage Current GND V
I
V
DDQ
2– 2A
I
OZ
Output Leakage Current GND V
I
V
DDQ,
Output Disabled 2– 2A
V
REF
Input Reference Voltage
[25]
Typical Value = 0.75 V 0.68 0.75 0.95 V
Notes
20. Overshoot: V
IH(AC)
< V
DDQ
+ 0.35 V (Pulse width less than t
CYC
/2), Undershoot: V
IL(AC)
> 0.3 V (Pulse width less than t
CYC
/2).
21. Power up: Assumes a linear ramp from 0 V to V
DD(min)
within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
22. All Voltage referenced to Ground.
23. Output are impedance controlled. I
OH
= (V
DDQ
/2)/(RQ/5) for values of 175 ohms < RQ < 350 ohms.
24. Output are impedance controlled. I
OL
= (V
DDQ
/2)/(RQ/5) for values of 175 ohms < RQ < 350 ohms.
25. V
REF(min)
= 0.68V or 0.46V
DDQ
, whichever is larger, V
REF
(max) = 0.95V or 0.54V
DDQ
, whichever is smaller.
CY7C15632KV18
Document Number: 001-54932 Rev. *K Page 21 of 30
I
DD
[26]
V
DD
Operating Supply V
DD
= Max, I
OUT
= 0 mA, f
= f
MAX
= 1/t
CYC
500 MHz – – 850 mA
450 MHz – – 780 mA
400 MHz – – 710 mA
I
SB1
Automatic Power down Current Max V
DD
,
Both Ports Deselected,
V
IN
V
IH
or V
IN
V
IL
f = f
MAX
= 1/t
CYC
,
Inputs Static
500 MHz – – 360 mA
450 MHz – – 340 mA
400 MHz – – 320 mA
AC Electrical Characteristics
Over the Operating Range
Parameter
[27]
Description Test Conditions Min Typ Max Unit
V
IH
Input HIGH Voltage V
REF
+ 0.2 – V
DDQ
+ 0.24 V
V
IL
Input LOW Voltage –0.24 – V
REF
– 0.2 V
Capacitance
Parameter
[28]
Description Test Conditions Max Unit
C
IN
Input capacitance T
A
= 25 C, f = 1 MHz, V
DD
= 1.8 V, V
DDQ
= 1.5 V 4 pF
C
O
Output capacitance 4pF
Thermal Resistance
Parameter
[28]
Description Test Conditions
165-ball FBGA
Package
Unit
JA
(0 m/s) Thermal resistance
(junction to ambient)
Socketed on a 170 × 220 × 2.35 mm, eight-layer printed
circuit board
14.43 °C/W
JA
(1 m/s) 13.40 °C/W
JA
(3 m/s) 12.66 °C/W
JB
Thermal resistance
(junction to board)
11.38 °C/W
JC
Thermal resistance
(junction to case)
3.30 °C/W
Electrical Characteristics (continued)
Over the Operating Range
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
[22]
Description Test Conditions Min Typ Max Unit
Notes
26. The operation current is calculated with 50% read cycle and 50% write cycle.
27. Overshoot: V
IH(AC)
< V
DDQ
+ 0.35 V (Pulse width less than t
CYC
/2), Undershoot: V
IL(AC)
> 0.3 V (Pulse width less than t
CYC
/2).
28. Tested initially and after any design or process change that may affect these parameters.
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CY7C15632KV18-450BZXC

Mfr. #:
Buy CY7C15632KV18-450BZXC
Manufacturer:
Cypress Semiconductor
Description:
SRAM 72MB (4Mx18) 1.8v 450MHz QDR II SRAM
Lifecycle:
New from this manufacturer.
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