Document Number: 001-54932 Rev. *K Page 23 of 30
Switching Characteristics
Over the Operating Range
Parameters
[30, 31]
Description
500 MHz 450 MHz 400 MHz
Unit
Cypress
Parameter
Consortium
Parameter
Min Max Min Max Min Max
t
POWER
V
DD
(typical) to the First Access
[32]
1–1–1–ms
t
CYC
t
KHKH
K Clock Cycle Time 2.0 8.4 2.2 8.4 2.5 8.4 ns
t
KH
t
KHKL
Input Clock (K/K) HIGH
0.4–0.4–0.4–ns
t
KL
t
KLKH
Input Clock (K/K) LOW
0.4–0.4–0.4–ns
t
KHKH
t
KHKH
K Clock Rise to K Clock Rise (rising edge to rising
edge)
0.85 – 0.94 – 1.06 – ns
Setup Times
t
SA
t
AVKH
Address Setup to K Clock Rise 0.25 – 0.275 – 0.4 – ns
t
SC
t
IVKH
Control Setup to K Clock Rise (RPS, WPS)
0.25 – 0.275 – 0.4 – ns
t
SCDDR
t
IVKH
Double Data Rate Control Setup to Clock (K/K) Rise
(BWS
0
, BWS
1
,
BWS
2
, BWS
3
)
0.20 – 0.22 – 0.28 – ns
t
SD
t
DVKH
D
[X:0]
Setup to Clock (K/K) Rise
0.20 – 0.22 – 0.28 – ns
Hold Times
t
HA
t
KHAX
Address Hold after K Clock Rise
0.25 – 0.275 – 0.4 – ns
t
HC
t
KHIX
Control Hold after K Clock Rise (RPS, WPS) 0.25 – 0.275 – 0.4 – ns
t
HCDDR
t
KHIX
Double Data Rate Control Hold after Clock (K/K) Rise
(BWS
0
, BWS
1
, BWS
2
, BWS
3
)
0.20 – 0.28 – 0.28 – ns
t
HD
t
KHDX
D
[X:0]
Hold after Clock (K/K) Rise
0.20 – 0.28 – 0.28 – ns
Output Times
t
CO
t
CHQV
K/K Clock Rise to Data Valid
–0.45–0.45–0.45ns
t
DOH
t
CHQX
Data Output Hold after Output K/K Clock Rise (Active
to Active)
–0.45 – –0.45 – –0.45 – ns
t
CCQO
t
CHCQV
K/K Clock Rise to Echo Clock Valid
–0.45–0.45–0.45ns
t
CQOH
t
CHCQX
Echo Clock Hold after K/K Clock Rise
–0.45 – –0.45 – –0.45 – ns
t
CQD
t
CQHQV
Echo Clock High to Data Valid – 0.15 – 0.15 – 0.20 ns
t
CQDOH
t
CQHQX
Echo Clock High to Data Invalid –0.15 – –0.15 – –0.20 – ns
t
CQH
t
CQHCQL
Output Clock (CQ/CQ) HIGH
[33]
0.75 – 0.85 – 1.0 – ns
t
CQHCQH
t
CQHCQH
CQ Clock Rise to CQ Clock Rise
(rising edge to rising
edge)
[33]
0.75 – 0.85 – 1.0 – ns
Notes
30. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, V
REF
= 0.75 V, RQ = 250 , V
DDQ
= 1.5 V,
input pulse levels of 0.25 V to 1.25 V, and output loading of the specified I
OL
/I
OH
and load capacitance shown in (a) of Figure 5 on page 22.
31. When a part with a maximum frequency above 400 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
32. This part has a voltage regulator internally; t
POWER
is the time that the power must be supplied above V
DD
minimum initially before a read or write operation can be
initiated.
33. These parameters are extrapolated from the input timing parameters (t
CYC
/2 – 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production.
