Document Number: 001-54932 Rev. *K Page 7 of 30
Concurrent Transactions
The read and write ports on the CY7C15632KV18 operates
completely independently of one another. As each port latches
the address inputs on different clock edges, the user can read or
write to any location, regardless of the transaction on the other
port. If the ports access the same location when a read follows a
write in successive clock cycles, the SRAM delivers the most
recent information associated with the specified address
location. This includes forwarding data from a write cycle that
was initiated on the previous K clock rise.
Read access and write access must be scheduled such that one
transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports are deselected, the
read port takes priority. If a read was initiated on the previous
cycle, the write port takes priority (as read operations cannot be
initiated on consecutive cycles). If a write was initiated on the
previous cycle, the read port takes priority (as write operations
can not be initiated on consecutive cycles). Therefore, asserting
both port selects active from a deselected state results in alter-
nating read or write operations being initiated, with the first
access being a read.
Depth Expansion
The CY7C15632KV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
SS
to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5 × the value of the
intended line impedance driven by the SRAM, the allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350
, with V
DDQ
=1.5V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR II+ to simplify data capture
on high-speed systems. Two echo clocks are generated by the
QDR II+. CQ is referenced with respect to K and CQ
is
referenced with respect to K. These are free running clocks and
are synchronized to the input clock of the QDR II+. The timing
for the echo clocks is shown in the Switching Characteristics on
page 23.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR II+ to simplify data capture on high
speed systems. The QVLD is generated by the QDR II+ device
along with data output. This signal is also edge-aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF
is tied HIGH, the PLL is locked after
20 s of stable clock. The PLL can also be reset by slowing or
stopping the input clocks K and K
for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF
pin. When the PLL is turned off, the device
behaves in QDR I mode (with one cycle latency and a longer
access time). For information, refer to the application note, PLL
Considerations in QDRII/DDRII/QDRII+/DDRII+.
