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16
Setting the Output Voltage (Adjustable Version)
The output voltage range of the adjustable version can be
set between 2.5 V and 20 V. This is accomplished with an
external resistor divider feeding back the voltage to the IC
back to the error amplifier by the voltage adjust pin VA.
The internal reference voltage is set to a temperature stable
reference of 2.5 V.
The output voltage is calculated from the following
formula. Ignoring the bias current into the VA pin:
V
Q
+ [(R1 ) R2) * V
ref
]ńR2
Use R2 < 50 k to avoid significant voltage output errors
due to VA bias current.
Connecting VA directly to Q without R1 and R2 creates
an output voltage of 2.5 V.
Designers should consider the tolerance of R1 and R2
during the design phase.
The input voltage range for operation (pin 1) of the
adjustable version is between (V
Q
+ 0.5 V) and 40 V.
Internal bias requirements dictate a minimum input voltage
of 4.5 V. The dropout voltage for output voltages less than
4.0 V is (4.5 V V
Q
).
NCV4276, NCV4276A
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17
Calculating Power Dissipation
in a Single Output Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 50) is:
P
D(max)
+ [V
I(max)
* V
Q(min)
]I
Q(max)
(1)
) V
I(max)
I
q
where
V
I(max)
is the maximum input voltage,
V
Q(min)
is the minimum output voltage,
I
Q(max)
is the maximum output current for the
application,
I
q
is the quiescent current the regulator
consumes at I
Q(max)
.
Once the value of P
D(max)
is known, the maximum
permissible value of R
q
JA
can be calculated:
R
qJA
+
150
o
C *
T
A
P
D
(2)
The value of R
q
JA
can then be compared with those in the
package section of the data sheet. Those packages with
R
q
JA
less than the calculated value in Equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
SMART
REGULATOR®
Iq
Control
Features
I
Q
I
I
Figure 50. Single Output Regulator with Key
Performance Parameters Labeled
V
I
V
Q
}
Heatsinks
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and
the outside environment will have a thermal resistance.
Like series electrical resistances, these resistances are
summed to determine the value of R
q
JA
:
R
qJA
+ R
qJC
) R
qCS
) R
qSA
(3)
where
R
q
JC
is the junctiontocase thermal resistance,
R
q
CS
is the casetoheatsink thermal resistance,
R
q
SA
is the heatsinktoambient thermal
resistance.
R
q
JC
appears in the package section of the data sheet.
Like R
q
JA
, it too is a function of package type. R
q
CS
and
R
q
SA
are functions of the package type, heatsink and the
interface between them. These values appear in data sheets
of heatsink manufacturers.
Thermal, mounting, and heatsinking considerations are
discussed in the ON Semiconductor application note
AN1040/D.
NCV4276, NCV4276A
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18
Thermal Model
A discussion of thermal modeling is in the ON Semiconductor web site: http://www.onsemi.com/pub/collateral/BR1487D.PDF.
Table 1. DPAK 5Lead Thermal RC Network Models
Drain Copper Area (1 oz thick) 168 mm
2
736 mm
2
168 mm
2
736 mm
2
(SPICE Deck Format) Cauer Network Foster Network
168 mm
2
736 mm
2
Units Ta u Ta u Units
C_C1 Junction GND 1.00E06 1.00E06 Ws/C 1.36E08 1.361E08 sec
C_C2 node1 GND 1.00E05 1.00E05 Ws/C 7.41E07 7.411E07 sec
C_C3 node2 GND 6.00E05 6.00E05 Ws/C 1.04E05 1.029E05 sec
C_C4 node3 GND 1.00E04 1.00E04 Ws/C 3.91E05 3.737E05 sec
C_C5 node4 GND 4.36E04 3.64E04 Ws/C 1.80E03 1.376E03 sec
C_C6 node5 GND 6.77E02 1.92E02 Ws/C 3.77E01 2.851E02 sec
C_C7 node6 GND 1.51E01 1.27E01 Ws/C 3.79E+00 9.475E01 sec
C_C8 node7 GND 4.80E01 1.018 Ws/C 2.65E+01 1.173E+01 sec
C_C9 node8 GND 3.740 2.955 Ws/C 8.71E+01 8.59E+01 sec
C_C10 node9 GND 10.322 0.438 Ws/C sec
168 mm
2
736 mm
2
R’s R’s
R_R1 Junction node1 0.015 0.015 C/W 0.0123 0.0123 C/W
R_R2 node1 node2 0.08 0.08 C/W 0.0585 0.0585 C/W
R_R3 node2 node3 0.4 0.4 C/W 0.0304 0.0287 C/W
R_R4 node3 node4 0.2 0.2 C/W 0.3997 0.3772 C/W
R_R5 node4 node5 2.97519 2.6171 C/W 3.115 2.68 C/W
R_R6 node5 node6 8.2971 1.6778 C/W 3.571 1.38 C/W
R_R7 node6 node7 25.9805 7.4246 C/W 12.851 5.92 C/W
R_R8 node7 node8 46.5192 14.9320 C/W 35.471 7.39 C/W
R_R9 node8 node9 17.7808 19.2560 C/W 46.741 28.94 C/W
R_R10 node9 GND 0.1 0.1758 C/W C/W
NOTE: Bold face items represent the package without the external thermal system.
Junction
R
1
C
1
C
2
R
2
C
3
R
3
C
n
R
n
Time constants are not simple RC products. Amplitudes
of mathematical solution are not the resistance values.
Ambient
(thermal ground)
Figure 51. Grounded Capacitor Thermal Network (“Cauer” Ladder)
Junction
R
1
C
1
C
2
R
2
C
3
R
3
C
n
R
n
Each rung is exactly characterized by its RCproduct
time constant; amplitudes are the resistances.
Ambient
(thermal ground)
Figure 52. NonGrounded Capacitor Thermal Ladder (“Foster” Ladder)

NCV4276DSADJG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC REG LIN POS ADJ 400MA D2PAK-5
Lifecycle:
New from this manufacturer.
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