UBA20260 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 10 October 2011 13 of 30
NXP Semiconductors
UBA20260
600 V driver IC for step dimmable CFLs
Four internal references determine the actual internal set point levels used for the different
step dim levels. Depending on the selected dim level, the current control feedback loop
regulates the voltage on the CSI pin. In this way, it ensures that V
i(CSI)
is equal to one of
the selected internal set point voltages. The sequence of the four dim steps shown in
Figure 11
is as follows:
The lamp is switched off longer than the memory retention time: the IC starts up in the
DIM_1 mode (lamp is 100 % on, no dimming)
After lamp off/on toggling, the IC twice enters the DIM_2 mode: the lamp is dimmed to
approximately 66 %
(1)
of its initial light output
The next lamp off/on toggling, the IC enters the DIM_3 mode: the lamp is dimmed
approximately 33 %
(1)
of its initial light output
Toggling the lamp off/on again: the IC enters the MDL (Minimum Dimming Level)
mode. This level equals approximately 10 %
(1)
of the initial light output
Renewed toggling enters the DIM_1 mode again.
Where
(1)
= R
MDL
= 2 k
Fig 10. Supply voltage cycle for dim step change
0
V
DD(rst)
V
ret(dim)CP
V
DD(stop)
V
DD(start)
5
lamp on
old dim level
lamp on
new dim level
dim step
change
lamp off
V
DD
V
CP
voltage
(V)
time (s)
001aam769
start-upretention
UBA20260 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 10 October 2011 14 of 30
NXP Semiconductors
UBA20260
600 V driver IC for step dimmable CFLs
As the internal step reference voltages are independent from the mains voltage, the lamp
current output is kept constant. Making the lamp current output not susceptible to line
voltage fluctuations. The MDL level sets the minimum lamp current level and is adjusted
using the MDL pin. An accurate minimum dimming voltage level is set using an internal
reference current and an external resistor R
MDL
. The internal reference current is derived
from the internal band gap reference circuit and resistor R
ext(RREF)
. The other two step
dimming levels are set at a fixed voltage offset referenced to the adjusted MDL level. This
means that these levels shift by the same voltage as the MDL shifts. When the MDL level
is at the default level, the light output in DIM_2, DIM_3 and MDL modes is approximately
66 %, 33 % and 5 % from nominal.
7.5 Protection functions and Power-down mode
7.5.1 Coil saturation protection
CSP is integrated into the IC to allow the use of small CFL lamps and use of small coils.
Saturation of these coils is detected and excessive overcurrent due to saturation is
prevented. CSP is only enabled during the ignition state. A cycle-by-cycle control
mechanism is used to limit voltages and currents in the resonant circuit when there is no
or delayed ignition. It prevents coil saturation, limits high peak currents and the dissipation
in the half-bridge power transistors.
Coil saturation is detected by monitoring the voltage across the R
SLS
resistor. A trigger is
generated when this voltage exceeds the V
th(sat)SLS
level. When saturation is detected, a
fixed current I
o(sat)CF
is injected into the C
CF
capacitor to shorten the half-bridge
Fig 11. Voltage on pin CSI as function of dim step
0
001aam770
1.2
1.0
0.8
0.6
0.2
V
i(CSI)
= V
MDL
V
clamp(CSI)
Internal clamp
V
DD
off-on toggle
∆V
dim2(CSI)
V
DD
off-on toggle
(1) = V
DD
off-on toggle
∆V
dim3(CSI)
V
i(CSI)
V
RMS
0.4
DIM_2
DIM_1
100 %
DIM_3
MDL
(1)
(1)
UBA20260 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 10 October 2011 15 of 30
NXP Semiconductors
UBA20260
600 V driver IC for step dimmable CFLs
switching cycle. The injected current is maintained until the end of the switching cycle.
This action immediately increases the half-bridge switching frequency. Additionally, for
each successive cycle that coil saturation is detected, capacitor C
CI
discharges enabling
ignition time-out detection in the ignition state.
CSP is triggered when the voltage on the SLS pin exceeds V
th(sat)SLS
(typically 2.5 V). The
voltage V
i(SLS)
on the SLS pin is determined by the external resistor R
SLS
value and also
sets the preheat current.
7.5.2 Overcurrent protection
OCP is active in both the burn and boost states but not during boost transition.
Overcurrent is detected, when the peak voltage of the absolute value across the current
sense resistor connected to the SLS pin exceeds the OCP reference level V
th(ocp)SLS
. A
current I
o(CP)
is then sunk from the capacitor connected to the CP pin for the next full
cycle.
If overcurrent is not present at the end of this cycle, the current is disabled. A current,
equal to I
o(CP)
is sourced to the CP pin instead. If overcurrent occurs in more than half the
number of cycles, a net discharging of the capacitor connected to the CP pin occurs.
When the voltage on the CP pin drops below V
th(CP)min
, the IC enters Power-down mode.
During a continuous overcurrent condition, the overcurrent fault time of t
fault(oc)
takes
1
9
t
ph
after which the IC enters Power-down mode. The V
th(ocp)SLS
level is the same as
the V
th(sat)SLS
level during the ignition state.
7.5.3 Overpower protection
OPP is active in the boost and burn state. The lamp current is limited and regulated in all
dim step states to the internal dim step reference voltage levels. These reference voltage
levels are derived from an internal reference voltage. Consequently, supply voltage
fluctuations in the mains supply voltage during overvoltage situations do not affect these
reference voltage levels.
When the lamp is in the first dim mode (no dimming), the current is limited and regulated
to the nominal lamp current. In addition, in the boost state the first dim mode boosted by a
factor of 1.5.
7.5.4 Capacitive mode protection
CMP is active in the ignition, burn and boost states and during boost transition. The signal
across resistor R
SLS
also provides information about the half-bridge switching behavior.
When conditions are normal, the current flows from the LS transistor source to the
half-bridge when the LS transistor is switched on. This results in a negative voltage on the
SLS pin.
As the circuit yields to capacitive mode, the voltage becomes smaller and eventually
reverses polarity. CMP prevents this action by checking if the voltage on the SLS pin is
above the V
th(capm)SLS
level.
If the voltage across resistor R
SLS
is above the V
th(capm)SLS
threshold when the LS
transistor is switched on, the circuit recognizes it as capacitive mode. When capacitive
mode is detected, the currents from the OTA, which normally regulate the lamp current,
are disabled. Then the capacitive mode sink current I
o(CI)
is enabled.

UBA20260T/1,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC CFL LAMP DVR 600V 16-SOIC
Lifecycle:
New from this manufacturer.
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