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M2004-02I622.0800

P1-P3P4-P6P7-P9P10-P10
M2004-02/-12 Datasheet Rev 1.3 Revised 17Dec2004
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M2004-02/-12
FREQUENCY TRANSLATION PLL
Integrated
Circuit
Systems, Inc.
Product Data Sheet
GENERAL DESCRIPTION
The M2004 variants -02 and -12 are VCSO (Voltage
Controlled SAW Oscillator) based
clock generator PLLs designed for
clock frequency translation and jitter
attenuation in a high-speed data
communications system. The clock
multiplication ratio and output
divider ratio are pin selectable.
External loop components allow the tailoring of PLL
loop response. The M2004-12 adds Hitless Switching
with Phase Build-out (HS/PBO) to ensure that reference
clock reselection does not disrupt the output clock.
Also read about device variants -22, -32, -42, and
-52 in the M2004-x2 Preliminary Information sheet.
FEATURES
◆ Ideal for OC-48/192 data clock
◆ Integrated SAW (surface acoustic wave) delay line
◆ VCSO frequency from 300 to 700MHz
(Specify VCSO center frequency at time of order)
◆ Low phase jitter of < 0.5ps rms, typical (12kHz to
20MHz or 50kHz to 80MHz)
◆ Pin-selectable configuration
◆ The M2004-12 adds Hitless Switching with Phase
Build-out (HS/PBO) to ensure SONET/SDH MTIE and
TDEV compliance during reference clock reselection
◆ Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆ Industrial temperature available
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
SIMPLIFIED BLOCK DIAGRAM
Figure 2: Simplified Block Diagram
Example Input / Output Frequency Combinations
Input Clock
(MHz)
VCSO
1
Freq (MHz)
Note 1: Specify VCSO center frequency at time of order
Output
Freq (MHz)
Application
19.44
622.08
77.76
OC-12 / 48 /192
38.80 155.52
77.76 311.04
155.52 622.08
25.00 625.00 156.25 Gigabit Ethernet
Table 1: Example Input / Output Frequency Combinations
M2004-02
M2004-12
(Top View)
18
17
16
15
14
13
12
11
10
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
M0
GND
REF_CLK
DIF_REF
nDIF_REF
REF_SEL
NC
NC
VCC
NC
MR
nFOUT
FOUT
GND
N1
N0
VCC
GND
M1
M2
M3
M4
M5
VCC
DNC
DNC
DNC
nOP_IN
OP_OUT
VC
nVC
nOP_OUT
OP_IN
GND
GND
GND
19
20
21
22
23
24
25
26
27
REF_SEL
DIF_REF
REF_CLK
0
M2004-02/-12
FOUT
nFOUT
M Divider
N Divider
VCSO
1
6
M5:0 N1:0
2
MR
nDIF_REF
Loop
Filter
M2004-02/-12 Frequency Translation PLL
M2004-02/-12 Datasheet Rev 1.3 2 of 10 Revised 17Dec2004
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M2004-02/-12
F
REQUENCY
T
RANSLATION
PLL
Product Data Sheet
PIN DESCRIPTIONS
Number Name I/O Configuration Description
1, 2, 3, 10, 14, 26 GND
Ground Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections. See Figure 4,
External Loop Filter, on pg. 5.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 19, 33 VCC
Power Power supply connection, connect to +3.3V.
12
13
N0
N1
Input Internal pull-down resistor
1
Note 1: For typical values of internal pull-down and pull-up resistors, see DC Characteristics on pg. 6.
N divider (output divider) inputs N1:N0.
LVCMOS/LVTTL. See Table 5, N Divider Pin
Selection
, on pg. 3.
15
16
FOUT
nFOUT
Output No internal terminator Clock output pair. Differential LVPECL.
17 MR
Input Internal pull-down resistor
1
Reset:
Logic
1 resets M and N dividers and forces
FOUT to LOW and nFOUT to HIGH.
Logic
0 enables the outputs.
LVCMOS/LVTTL.
18
20
21
NC
NC
NC
No connection.
22 REF_SEL
Input Internal pull-down resistor
1
Referenc
e clock input selection.
LVCMOS/LVTTL.
See Table 3, Reference Clock Input Selection,
on
pg. 3. For the M2004-12, REF_SEL triggers Hitless
Switching (HS/PBO) when toggled.
23
24
nDIF_REF
Input
Internal pull-UP resistor
1
Reference clock input pair.
Differential LVPECL or LVDS.
DIF_REF
Internal pull-down resistor
1
25 REF_CLK
Input Internal pull-down resistor
1
Reference clock input. LVCMOS/LVTTL.
27
28
29
30
31
M0
M1
M2
M3
M4
Input
Internal pull-down resistor
1
M divider (feedback divider) inputs M5:M0.
See Table 4, M Divider Pin Selection, on pg. 3.
32 M5
Internal pull-UP resistor
1
34, 35, 36 DNC
Do Not Connect.
Table 2: Pin Descriptions
M2004-02/-12 Datasheet Rev 1.3 3 of 10 Revised 17Dec2004
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M2004-02/-12
F
REQUENCY
T
RANSLATION
PLL
Product Data Sheet
Integrated
Circuit
Systems, Inc.
DETAILED BLOCK DIAGRAM
Figure 3: Detailed Block Diagram
PLL DIVIDER SELECTION TABLES
Reference Clock Input Selection
M Divider Pin Selection
N Divider Pin Selection
M2004-02
M2004-12
SAW Delay Line
Phase
Shifter
VCSO
C
POST
C
POST
VCnVC
R
POST
nOP_OUTOP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
R
IN
R
IN
OP_IN nOP_IN
M Divider
M = 3-63
MUX
1
0
N Divider
N = 1,2,4,8
Pin Configuration Register
6
M5:0 N1:0
Phase
Detector
Loop Filter
Amplifier
External
Loop Filter
Components
REF_SEL
REF_CLK
FOUT
nFOUT
MR
2
DIF_REF
nDIF_REF
REF_SEL
Pin Setting
(Pin 22)
Reference Input Selection
0 DIF_REF, nDIF_REF
1
REF_CLK
Table 3: Reference Clock Input Selection
M5:0 Pin
Settings
(Pins 32 - 27)
M5 - M0
Definition
Sample Input Clock
Freq (MHz)
F
VCSO
= F
VCSO
=
622.08
1
, 625.00
2
Note 1: F
VCSO
= 622.08 MHz (e.g., M2004-02-622.0800)
Note 2: F
VCSO
= 625.00 MHz (e.g., M2004-02-625.0000)
5
3
4 3 2 1 0
Note 3: M5 pin has a pull-up resister; M4-M0, pull-down.
Feedback Divider Value “M”
0 0 0 0 1 1 M = 3 minimum
0 0 0 1 0 0
M = 4 155.52 156.25
0 0 1 0 0 0 M = 8 77.76
0 1 0 0 0 0
M = 16 38.80
0 1 1 0 0 1 M = 25 25.00
1 0 0 0 0 0 M = 32 19.44
1 1 1 1 1 1
M = 63
Table 4: M Divider Pin Selection
N1:0 Settings
(Pin 13 and 12)
N1 N0
N Divider
Value
Sample Output
Frequency (MHz)
1
(FOUT, nFOUT)
Note 1: F
VCSO
= 622.08MHz (e.g., M2004-02-622.0800)
0 0 1 622.08
0 1 2 311.04
1 0 4 155.52
1 1 8 77.76
Table 5: N Divider Pin Selection
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P1-P3P4-P6P7-P9P10-P10

M2004-02I622.0800

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IC PLL FREQ TRANSLATOR 36CLCC
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