M2004-02/-12 Datasheet Rev 1.3 5 of 10 Revised 17Dec2004
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M2004-02/-12
F
REQUENCY
T
RANSLATION
PLL
Product Data Sheet
Integrated
Circuit
Systems, Inc.
Hitless Switching and Phase Build-out
*
A proprietary automatic Hitless Switching (HS) function
is included in the M2004-12. The HS function provides
SONET/SDH MTIE and TDEV compliance during a
reference clock reselection using the internal mux or
when using an external mux (through detection of the
resulting phase transient).
**
A Phase Build-out (PBO)
function is also incorporated to absorb most of the
phase change in the reference clock input.
The combined HS/PBO function is armed after the
device locks to the input clock reference. Once armed,
HS/PBO is triggered by either:
• Changing REF_SEL to switch the input reference clock.
• Detection at the phase detector of an input phase
transient beyond 4 ns.
Once triggered, the HS function narrows loop band-
width to control MTIE during locking to the new input
phase. With proper configuration of the external loop
filter, the output clocks will comply with MTIE and TDEV
specifications for GR-253 (SONET) and ITU G.813
(SDH) during input reference clock changes.
The Phase Build-out (PBO) function enables the PLL to
absorb most of the phase change of the input clock.
The PBO function selects a new VCSO clock edge for
the phase detector feedback clock, selecting the edge
closest in phase to the new input clock phase. This
reduces re-lock time, the generation of wander, and
extra output clock cycles.
When the PLL locks to within 2 ns of the input clock
phase, the PLL returns to normal loop bandwidth and
the HS/PBO function is re-armed.
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M2004-02/-12 requires the use of an
external loop filter components. These are connected to
the provided filter pins (see Figure 4). Due to the
differential signal path design, the implementation
consists of two identical complementary RC filters as
shown in Figure 4, below.
Figure 4: External Loop Filter
PLL bandwidth is affected by the “M” value as well as
the VCSO frequency. See Table 6, External Loop Filter
Component Values M2004-02/-12, on pg. 5.
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
Note *: The M2004-02 does not include HS/PBO.
Note **:Transient-triggered HS/PBO is not suitable for use with an
unstable reference clock that would induce phase jitter
beyond 2 ns at the phase detector (e.g., Stratum DPLL clock
sources and unstable recovered network clocks intended for
loop timing configuration). Therefore, the M2004-12 also
offers the internal mux-triggered HS/PBO capability.
C
POST
C
POST
V
nVC
R
POST
nOP_OUTOP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN nOP_IN
6 7549 8
External Loop Filter Component Values
1
M2004-02/-12
VCSO Parameters: K
VCO
= 800kHz/V, R
IN
= 16k
Ω
, VCSO Bandwidth = 700kHz. See AC Characteristics on pg. 7 for PLL Loop Constants.
Device Configuration Example External Loop Filter Component Values Nominal Performance Using These Values
F
Ref
(MHz)
F
VCSO
(MHz)
M Divider
Value
R loop C loop R post C post PLL Loop
Bandwidth
Damping
Factor
Passband
Peaking (dB)
19.44 622.08 32
13kΩ 0.47µF 33kΩ 220pF 3.8kHz
5.6 0.06
19.44 622.08 32
39kΩ 0.022µF 20kΩ 220pF 12.7kHz
7.7 0.03
19.44 622.08 32
2.2kΩ 10.0µF 22kΩ 3300pF 710Hz
4.4 0.10
155.52 622.08 4
3.9kΩ 0.47µF 39kΩ 100pF 11.0kHz
4.7 0.09
155.52 622.08 4
750Ω 10.0µF 7.5kΩ 1000pF 1.6kHz
4.2 0.10
Table 6: External Loop Filter Component Values M2004-02/-12
Note 1: K
VCO
, VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping
Factor, and Passband Peaking. For PLL Simulator software, go to www.icst.com.
