M2004-02I622.0800

M2004-02/-12 Datasheet Rev 1.3 7 of 10 Revised 17Dec2004
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400
M2004-02/-12
F
REQUENCY
T
RANSLATION
PLL
Product Data Sheet
Integrated
Circuit
Systems, Inc.
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, V
CC
=
3.3
V +
5
%,T
A
=
0
o
C
to +
70
o
C (commercial), F
VCSO
= F
OUT
=
622-675
MHz, Outputs terminated with
50
to V
CC
- 2V
T
A
=
-40
o
C
to +
85
o
C (industrial)
Symbol Parameter Min Typ Max Unit Conditions
F
IN
Input Frequency
DIF_REF, nDIF_REF, REF_CLK 1 175
MHz
F
OUT
Output Frequency
FOUT, nFOUT
38 700
MHz
APR VCSO Pull-Range
Commercial
±120 ±200 ppm
Industrial
±50 ±150 ppm
PLL Loop
Constants
1
Note 1: Parameters needed for PLL Simulator software; see Table 6, External Loop Filter Component Values M2004-02/-12 on pg. 5.
K
VCO
VCO Gain 800 kHz/V
R
IN
Internal Loop Resistor
16
k
BW
VCSO
VCSO Bandwidth 700 kHz
Phase Noise
and Jitter
Φ n Single Side Band
Phase Noise
@
622.08MHz
1kHz Offset -72 dBc/Hz
10kHz Offset -94 dBc/Hz
100kHz Offset -123 dBc/Hz
J(t) Jitter (rms) 12kHz to 20MHz
0.5
ps
50kHz to 80MHz
0.5
ps
odc Output Duty Cycle
2
Note 2: See Parameter Measurement Information below.
N = 2, 4, or 8
45 50 55
%
N = 1
40 50 60
%
N = 1, using AC coupled LVPECL output
circuit as shown in Figure 8, page 8
45 50 55
%
t
R
Output Rise Time
2
for
FOUT,
nFOUT
F
OUT
=155.52MHz N = 4 (N1:0 = 10)
350 450 550
ps
20%
to
80%
F
OUT
=311.04MHz N = 2 (N1:0 = 01)
325 425 500
ps
F
OUT
=622.08MHz N = 1 (N1:0 = 00)
200 275 350
ps
t
F
Output Fall Time
2
for
FOUT,
nFOUT
F
OUT
=155.52MHz N = 4 (N1:0 = 10)
350 450 550
ps
20%
to
80%
F
OUT
=311.04MHz N = 2 (N1:0 = 01)
325 425 500
ps
F
OUT
=622.08MHz N = 1 (N1:0 = 00)
200 275 350
ps
t
LOCK
PLL Lock Time
100
ms
MTIE Mean Time Interval Error
3
M2004-12
Note 3: Requires proper loop filter settings. Consult factory.
Compliant with GR-253-CORE
Table 10: AC Characteristics
M2004-02/-12 Datasheet Rev 1.3 8 of 10 Revised 17Dec2004
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M2004-02/-12
F
REQUENCY
T
RANSLATION
PLL
Product Data Sheet
PARAMETER MEASUREMENT INFORMATION
Input and Output Rise and Fall Time
Figure 5: Input and Output Rise and Fall Time
Differential Input Level
Figure 6: Differential Input Level
Output Duty Cycle
Figure 7: Output Duty Cycle
AC Coupled LVPECL Output Circuit for 45-55% Duty Cycle at Fvco
Figure 8: AC Coupled Output
AC coupled termination can be used with the M2004-02/-12 LVPECL output, as shown above in Figure 8, to achieve an improved output
duty cycle of 45-55% or better at the load when N=1 (output N Divider). This performance has been characterized when R1 = R2 = 200,
C1 = C2 = 0.1µF, and when termination resistance at the receiver (combination of R3 with R5, and R4 with R6) is 50 ohms.
20%
80%
t
R
20%
t
F
80%
Clock Inputs
and Outputs
V
P-P
V
CC
- 0.85
nDIF_CLK
DIF_CLK
Cross Points
V
P-P
V
CMR
+ 0.5
nFOUT
FOUT
t
PW
t
PERIOD
(Output Pulse Width)
t
PERIOD
t
PW
odc =
ICS 3.3V LVPECL Driver Clock Receiver
R2
200
R1
200
R6
84
R5
84
R4
125
R3
125
Z
O
=50
Z
O
=50
C2
0.1 F
3.3V
C1
0.1 F
M2004-02/-12 Datasheet Rev 1.3 9 of 10 Revised 17Dec2004
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400
M2004-02/-12
F
REQUENCY
T
RANSLATION
PLL
Product Data Sheet
Integrated
Circuit
Systems, Inc.
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Figure 9: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier

M2004-02I622.0800

Mfr. #:
Manufacturer:
Description:
IC PLL FREQ TRANSLATOR 36CLCC
Lifecycle:
New from this manufacturer.
Delivery:
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