IXYS Reserves the Right to Change Limits, Test Conditions, and Dimensions.
IXYK30N170CV1
IXYX30N170CV1
IXYS MOSFETs and IGBTs are covered 4,835,592 4,931,844 5,049,961 5,237,481 6,162,665 6,404,065 B1 6,683,344 6,727,585 7,005,734 B2 7,157,338B2
by one or more of the following U.S. patents: 4,860,072 5,017,508 5,063,307 5,381,025 6,259,123 B1 6,534,343 6,710,405 B2 6,759,692 7,063,975 B2
4,881,106 5,034,796 5,187,117 5,486,715 6,306,728 B1 6,583,505 6,710,463 6,771,478 B2 7,071,537
Notes:
1. Pulse test, t 300μs, duty cycle, d 2%.
2. Switching times & energy losses may increase for higher V
CE
(clamp), T
J
or R
G
.
Reverse Diode (FRED)
(T
J
= 25°C, Unless Otherwise Specified) Characteristic Value
Symbol Test Conditions Min. Typ. Max.
V
F
3.5 V
T
J
= 150°C 3.7 V
I
RM
32 A
t
rr
175 ns
R
thJC
0.36°C/W
I
F
= 30A,V
GE
= 0V, -di
F
/dt = 500A/μs,
V
R
= 1200V, T
J
= 150°C
I
F
= 30A,V
GE
= 0V, Note 1
Symbol Test Conditions Characteristic Values
(T
J
= 25°C Unless Otherwise Specified) Min. Typ. Max.
g
fs
I
C
= 30A, V
CE
= 10V, Note 1 17 28 S
R
Gi
Gate Input Resistance 2.8
C
ie
s
3100 pF
C
oes
V
CE
= 25V, V
GE
= 0V, f = 1MHz 210 pF
C
res
55 pF
Q
g(on)
150 nC
Q
ge
I
C
= 30A, V
GE
= 15V, V
CE
= 0.5 • V
CES
15 nC
Q
gc
65 nC
t
d(on)
16 ns
t
ri
33 ns
E
on
3.6 mJ
t
d(off)
143 ns
t
fi
95 ns
E
of
f
1.8 mJ
t
d(on)
16 ns
t
ri
33 ns
E
on
5.5 mJ
t
d(off)
193 ns
t
fi
134 ns
E
off
3.5 mJ
R
thJC
0.16 °C/W
R
thCS
0.15 °C/W
Inductive load, T
J
= 25°C
I
C
= 30A, V
GE
= 15V
V
CE
= 0.5 • V
CES
, R
G
= 2.7
Note 2
Inductive load, T
J
= 150°C
I
C
= 30A, V
GE
= 15V
V
CE
= 0.5 • V
CES
, R
G
= 2.7
Note 2
PRELIMINARY TECHNICAL INFORMATION
The product presented herein is under development. The Technical Specifications offered are
derived from a subjective evaluation of the design, based upon prior knowledge and experi-
ence, and constitute a "considered reflection" of the anticipated result. IXYS reserves the right
to change limits, test conditions, and dimensions without notice.
Terminals: 1 - Gate
2,4 - Collector
3 - Emitter
PLUS 247
TM
Outline
TO-264 Outline
Terminals: 1 = Gate
2,4 = Colector
3 = Emitter
b
Q
D
R
E
A
S
R1
x2
b2
b1
A1
L1
31 2
L
c
e
4
0P
e
Q1
1 2 3
4
b
C
L
D
R
Q
E
A
A1
L1
D2
D1
E1
A2
b2 2 PLCS
3 PLCS
2 PLCS
b4
