LTC1605-1/LTC1605-2
11
160512fa
For more information www.linear.com/LTC1605-1
applicaTions inForMaTion
DIGITAL INTERFACE
Internal Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 7µs. No external adjustments
are required and, with the typical acquisition time of 1µs,
throughput performance of 100ksps is assured.
Timing and Control
Conversion start and data read are controlled by two
digital inputs: CS and R/C. To start a conversion and put
the sample-and-hold into the hold mode, bring CS and
R/C low for no less than 40ns.
Once initiated, it cannot
be restarted until the conversion is complete. Converter
status is indicated by the BUSY output and this is low
while the conversion is in progress.
There are two modes of operation. The first mode is shown
in Figure 8. The digital input R/C is used to control the
start of conversion. CS is tied low. When R/C goes low,
the sample-and-hold goes into the hold mode and a con
-
version is started. BUSY
goes low and stays low during
the conversion and will go back high after the conversion
has been completed and the internal output shift registers
have been updated
. R/C should remain low for no less than
40ns. During the time R/C is low, the digital outputs are in
a Hi-Z state. R/C should be brought back high within 3µs
after the start of the conversion to ensure that no errors
occur in the digitized result. The second mode, shown in
Figure 9, uses the CS signal to control the start of a con
-
version and the reading of the digital output. In this mode,
the R/
C input signal should be brought low no less than
10ns before the falling edge of CS. The minimum pulse
width for CS is 40ns. When CS falls, BUSY goes low and
will stay low until the end of the conversion. BUSY will go
high after the conversion has been completed. The new
data is valid when CS is brought back low again to initiate
a read. Again, it is recommended that both R/C and CS
return high within 3µs after the start of the conversion.
Output Data
The output data can be read as a 16-bit word or it can be
read as two 8-bit bytes. The format of the output data is
straight binary for the LTC1605-1 and two’s complement
for the LTC1605-2. The digital input pin BYTE is used to
control the two byte read. With the BYTE pin low, the first
eight MSBs are output on the D15 to D8 pins and the eight
LSBs are output on the D7 to D0 pins. When the BYTE
pin is taken high, the eight LSBs replace the eight MSBs
(Figure 10).
t
1
t
11
t
2
t
4
t
3
t
7
t
6
ACQUIRE CONVERT CONVERTACQUIRE
t
5
t
8
t
ACQ
t
CONV
t
9
PREVIOUS
DATA VALID
PREVIOUS
DATA VALID
HI-Z NOT VALID HI-Z
DATA
VALID
DATA
VALID
R/C
BUSY
MODE
DATA MODE
1605-1/2 F08
Figure 8. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low)
