LTC1605-1/LTC1605-2
7
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For more information www.linear.com/LTC1605-1
pin FuncTions
VIN (Pin 1): Analog Input. Connect through a 200Ω
resistor to the analog input. Full-scale input range is 0V
to 4V for the LTC1605-1 and ±4V for the LTC1605-2.
AGND1 (Pin 2): Analog Ground. Tie to analog ground
plane.
REF (Pin 3): 2.5V Reference Output. Bypass with 2.2µF
tantalum capacitor. Can be driven with an external refer
-
ence.
CAP (Pin 4
): Reference Buffer Output. Bypass with 2.2µF
tantalum capacitor.
AGND2 (Pin 5): Analog Ground. Tie to analog ground plane.
D15 to D8 (Pins 6 to 13): Three-State Data Outputs.
Hi-Z state when CS is high or when R/C is low.
DGND
(Pin 14):
Digital Ground.
D7 to D0 (Pins 15 to 22): Three-State Data Outputs.
Hi-Z state when CS is high or when R/C is low.
BYTE (Pin 23): Byte Select. With BYTE low, data will be
output with Pin 6 (D15) being the MSB and Pin 22 (D0)
being the LSB. With BYTE high the upper eight bits and
the lower eight bits will be switched. The MSB is output
on Pin 15 and bit 8 is output on Pin 22. Bit 7 is output on
Pin 6 and the LSB is output on Pin 13.
R/C (Pin 24): Read/Convert Input. With CS low, a falling
edge on R/C puts the internal sample-and-hold into the
hold state and starts a conversion. With CS low, a rising
edge on R/C enables the output data bits.
CS (Pin 25): Chip
Select. Internally ORd with R/C. With
R/C low, a falling edge on CS will initiate a conversion. With
R/C high, a falling edge on CS will enable the output data.
BUSY (Pin 26): Output Shows Converter Status. It is low
when a conversion is in progress. Data valid on the rising
edge of BUSY. CS or R/C must be high when BUSY rises
or another conversion will start without time for signal
acquisition.
V
ANA
(Pin 27): 5V Analog Supply. Bypass to ground with
a 0.1µF ceramic and a 10µF tantalum capacitor.
V
DIG
(Pin 28): 5V Digital Supply. Connect directly to
Pin27.
FuncTional block DiagraM
16-BIT CAPACITIVE DAC
COMPREF BUF
2.5V REF
CAP
(2.5V)
C
SAMPLE
C
SAMPLE
D15
D0
BUSY
CONTROL LOGIC
R/C BYTE
INTERNAL
CLOCK
CS
ZEROING SWITCHES
V
DIG
V
ANA
V
IN
REF
AGND1
AGND2
DGND
16
1605-1/2 BD
+
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT LATCHES
4k
4k
6K*
20k
3.75k*
10k
OPEN*
*RESISTOR VALUES FOR THE LTC1605-2
LTC1605-1/LTC1605-2
8
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For more information www.linear.com/LTC1605-1
TesT circuiTs
applicaTions inForMaTion
1k 50pF 50pF
DBN
DBN
1k
5V
1605-1/2 TC02
A. V
OH
TO HI-Z B. V
OL
TO HI-Z
Load Circuit for Access Timing
Load Circuit for Output Float Delay
1k C
L
C
L
DBN DBN
1k
5V
1605-1/2 TC01
A. HI-Z TO V
OH
AND V
OL
TO V
OH
B. HI-Z TO V
OL
AND V
OH
TO V
OL
autozero switch, S3. In this acquire phase, a minimum
delay of 2µs will provide enough time for the sample-and-
hold capacitor to acquire the analog signal. During the
convert phase
, S3 opens, putting the comparator into the
compare mode. The input switch S2 switches C
SAMPLE
to ground, injecting the analog input charge onto the
summing junction. This input charge is successively
compared with the binary-weighted charges supplied by
the capacitive DAC. Bit decisions are made by the high
speed comparator. At the end of a conversion, the DAC
output balances the V
IN
input charge. The SAR contents
(a 16-bit data word) that represents the V
IN
are loaded
into the 16-bit output latches.
Driving the Analog Inputs
The nominal input range for the LTC1605-1 is 0V to 4V or
(1.6V
REF
) and for the LTC1605-2 the input range is ±4V
or (±1.6V
REF
). The inputs are overvoltage protected to
±25V. The input impedance is typically 10kΩ; therefore,
it should be driven by a low impedance source. Wideband
noise coupling into the input can be minimized by placing
a 1000pF capacitor at the input as shown in Figure 2. An
NPO-type capacitor gives the lowest distortion. Place the
capacitor as close to the device input pin as possible. If
an amplifier is to be used to drive the input, care should
be taken to select an amplifier with adequate accuracy,
linearity and noise for the application. The following list
is a summary of the op amps that are suitable for driving
the LTC1605-1/LTC1605-2. More detailed information
is available in the Linear Technology data books and
LinearView
TM
CD-ROM.
Conversion Details
The LTC1605-1/LTC1605-2 use a successive approxima-
tion algorithm and an internal sample-and-hold circuit to
convert an analog signal to a 16-
bit or two byte parallel
output. The ADC is complete with a precision reference and
an internal clock. The control logic provides easy interface
to microprocessors and DSPs. (Please refer to the Digital
Interface section for the data format.)
Conversion start is controlled by the CS and R/C inputs.
At the start of conversion, the successive approximation
register (SAR) is reset. Once a conversion cycle has begun,
it cannot be restarted.
During the conversion, the internal 16-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, V
IN
is connected through the resistor divider
and S1 to the sample-and-hold capacitor during the
acquire phase and the comparator offset is nulled by the
Figure 1. LTC1605-1/LTC1605-2 Simplified Equivalent Circuit
V
DAC
1605-1/2 F01
+
C
DAC
DAC
S1
SAMPLE
S2
HOLD
C
SAMPLE
S
A
R
16-BIT
LATCH
COMPARATOR
SAMPLE
S3
R
IN2
R
IN1
V
IN
LinearView is a trademark of Linear Technology Corporation
LTC1605-1/LTC1605-2
9
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For more information www.linear.com/LTC1605-1
applicaTions inForMaTion
LT
®
1007 - Low noise precision amplifier. 2.7mA supply
current ±5V to ±15V supplies. Gain bandwidth product
8MHz. DC applications.
LT1097 - Low cost, low power precision amplifier. 300µA
supply current. ±5V to ±15V supplies. Gain bandwidth
product 0.7MHz. DC applications.
LT1227 - 140MHz video current feedback amplifier. 10mA
supply current. ±5V to ±15V supplies. Low noise and low
distortion.
LT1360 - 37MHz voltage feedback amplifier. 3.8mA supply
current. ±5V to ±15V supplies. Good AC/DC specs.
LT1363 - 50MHz voltage feedback amplifier. 6.3mA supply
current. Good AC/DC specs.
LT1364/LT1365 - Dual and quad 50MHz voltage feedback
amplifiers. 6.3mA supply current per amplifier. Good AC/
DC specs.
LT1468 - 90MHz, 22V/µs 16-Bit Accurate Amplifier
Internal Voltage Reference
The LTC1605-1/LTC1605-2 has an on-chip, temperature
compensated, curvature corrected, bandgap reference,
which is factory trimmed to 2.50V. The full-scale range
of the ADC is equal to (1.6V
REF
) or nominally 0V to 4V
for the LTC1605-1 and (±1.6V
REF
) or nominally ±4V for
the LTC1605-2. The output of the reference is connected
to the input of a unity-gain buffer through a 4k resistor
(see Figure 3). The input to the buffer or the output of the
reference is available at REF (Pin 3). The internal refer
-
ence can be overdriven with an external reference if more
accuracy is needed
.
The buffer output drives the internal
DAC and is available at CAP (Pin 4). The CAP pin can be
used to drive a steady DC load of less than 2mA. Driving
an AC load is not recommended because it can cause the
performance of the converter to degrade.
For minimum code transition noise the REF pin and the
CAP pin should each be decoupled with a capacitor to
filter wideband noise from the reference and the buffer
(2.2µF tantalum).
Offset and Gain Adjustments
The LTC1605-1/LTC1605-2 offset and full-scale er
-
rors have been trimmed at the factory with the external
resistors shown in Figure 4
.
This allows for external
adjustment of offset and full scale in applications where
absolute accuracy is important. See Figure 5 for the off
-
set and gain trim circuit for the LTC1605-1/LTC1605-2.
First adjust the offset to zero by adjusting resistor R3.
Apply an input voltage of
30.5µV
(0.5LSB) and adjust R3
so the code is changing between 0000 0000 0000 0001
and 0000 0000 0000 0000. The gain error is trimmed by
adjusting resistor R4. An input voltage of 3.999908V (FS
1.5LSB) is applied to V
IN
and R4 is adjusted until the
output code is changing between 1111 1111 1111 1110
and 1111 1111 1111 1111. Figure 6a shows the unipolar
transfer characteristic of the LTC1605-1.
For the LTC1605-2, first adjust the offset to zero by
adjusting resistor R3. Apply an input voltage of –61µV
(–0.5LSB) and adjust R3 so the code is changing between
1111 1111 1111 1111 and 0000 0000 0000 0000. The gain
error is trimmed by adjusting resistor R4. An input voltage
of 3.999817V (+FS – 1.5LSB) is applied to V
IN
and R4 is
adjusted until the output code is changing between 0111
1111 1111 1110 and 0111 1111 1111 1111. Figure 6b
shows the bipolar transfer characteristics of the LTC1605-2.
DC Performance
One way of measuring the transition noise associated with
a high resolution ADC is to use a technique where a DC
signal is applied to the input of the ADC and the result
-
ing output codes are collected over a large number of
conversions
.
For example, in Figure 7 the distribution of
output code is shown for a DC input that has been digitized
10000 times. The distribution is Gaussian and the RMS
code transition is about 1LSB.
1605-1/2 F02
1000pF 33.2k
V
IN
CAP
A
IN
200Ω
Figure 2. Analog Input Filtering

LTC1605-1CG#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 100ksps 16-Bit ADC 0V to 4V
Lifecycle:
New from this manufacturer.
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