LTC1605-1/LTC1605-2
13
160512fa
For more information www.linear.com/LTC1605-1
applicaTions inForMaTion
Dynamic Performance
FFT (Fast Fourier Transform) test techniques are used to
test the ADCs frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo
-
rithm, the ADCs spectral content can be examined for
frequencies outside the fundamental
.
Figure 11 shows a
typical LTC1605-2 FFT plot which yields a SINAD of 87dB
and THD of –101.1dB.
Signal-to-Noise Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 11 shows a typical SINAD of 87dB with
a 100kHz sampling rate and a 1kHz input.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = 20log
V2
2
+ V3
2
+ V4
2
...+ V
N
2
V1
FREQUENCY (kHz)
0
MAGNITUDE (dB)
1605-1/2 G07/F11
5 10 15 20 25 30 35 40 45 50
0
10
20
30
40
50
60
70
80
90
100
110
120
130
f
SAMPLE
= 100kHz
f
IN
= 1kHz
SINAD = 87dB
THD = 101.1dB
SNR = 87.2dB
Figure 11. LTC1605-2 Nonaveraged 4096-Point FFT Plot
where V1 is the RMS amplitude of the fundamental
frequency and V2 through V
N
are the amplitudes of the
second through Nth harmonics.
Board Layout, Power Supplies and Decoupling
Wire wrap boards are not recommended for high reso
-
lution or high speed A/D converters. To obtain the best
performance from the
LTC1605-1/LTC1605-2, a printed
circuit board is required. Layout for the printed circuit
board should ensure the digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by AGND.
Figures 12 through 15 show a layout for a suggested evalu
-
ation circuit which will help obtain the best performance
from the 16-bit ADC. Additional information regarding the
evaluation circuit and Gerber files for the PC board layout
are available from Linear Technology or your local sales
office. Pay particular attention to the design of the analog
and digital ground planes. The DGND pin of the LTC1605-1/
LTC1605-2 can be tied to the analog ground plane. Placing
the bypass capacitor as close as possible to the power
supply, the reference and reference buffer output is very
important. Low impedance common returns for these
bypass capacitors are essential to low noise operation of
the ADC, and the PC track width for these lines should be
as wide as possible. Also, since any potential difference in
grounds between the signal source and ADC appears as
an error voltage in series with the input signal, attention
should be paid to reducing the ground circuit impedance
as much as possible. The digital output latches and the
onboard sampling clock have been placed on the digital
ground plane. The two ground planes are tied together at
the power supply ground connection.
LTC1605-1/LTC1605-2
14
160512fa
For more information www.linear.com/LTC1605-1
applicaTions inForMaTion
Figure 12. Component Side Silkscreen for the Suggested LTC1605-1/LTC1605-2 Evaluation Circuit
ANALOG
GROUND PLANE
ANALOG
GROUND PLANE
DIGITAL
GROUND PLANE
Figure 13. Bottom Side Showing Analog Ground Plane
Figure 14. Component Side Showing Separate Analog
and Digital Ground Plane
LTC1605-1/LTC1605-2
15
160512fa
For more information www.linear.com/LTC1605-1
applicaTions inForMaTion
D15
+
3
U6A
74HC221
A
B
Q
Q
CEXT
R21, 2k
RCEXT
15
1
2
4
13
CLK
1605-1/2 F15
D15
D14
U1
LTC1605-1
LTC1605-2
D13
D12
D11
C5
0.1μF
R19
33.2k
1%
C3
0.1μF
C16
1000pF
C4
2.2μF
C2
2.2μF
EXT INTV
REF
JP1
C17
10μF
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
D0
D15 D15
D14
D13
D12
D11
D10
D9
D8
2
3
4
5
6
7
8
9
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
4
R20
1K
3
U4B
74HC04
65
U4C
74HC04
C1
15PF
22
1
2
3
4
5
14
23
24
25
26
27
28
V
IN
Q0
U2
74HC574
19
D0
Q1
18
D1
Q2
17
D2
Q3
16
D3
Q4
15
D4
Q5
14
D5
Q6
13
D6
Q7
1 2
12
U4A
74HC04
D7
1
OC
11
CLK
2
7
6
5
4
3
U7
74HC160
CLR
LOAD
RCO
15
2
3
JP3
1
EXT
CLK
INT
2
3
JP5
1
V
CC
CS
GND
ENP
10
ENT
QD
11
D
QC
12
C
QB
13
B
QA
14
A
2
U8
1MHz, OSC
OUT
3
GND
1
NA
E2
GND
V
IN
7V TO 15V
E1
U5
LT1121
D16
MBR0520
C6
22μF
10V
GND
1 3
2
V
IN
V
IN
4
U9
LT1019-2.5
TRIM
5
GND
1
NC1
2
INPUT
3
8
7
6
TEMP
NC2
HEATER
OUT
1
9
CLK
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
Q0
U3
74HC574
19
D0
Q1
18
D1
Q2
17
D2
Q3
16
D3
Q4
15
D4
Q5
14
D5
Q6
13
D6
Q7
12
D7
1
OC
11
CLK
AGND1
REF
CAP
AGND2
DGND
BYTE
R/C
CS
BUSY
V
ANA
V
DIG
C8
0.1μF
C7
10μF
V
KK
V
CC
V
KK
V
KK
V
DD
V
CC
R16
20
C9
0.1μF
C10
0.1μF
DIGITAL I.C. BYPASSING
C11
0.1μF
C12
0.1μF
V
CC
C13
0.1μF
C14
0.1μF
C15
10μF
2
3
JP4
1
REVERSE
BYTE
NORNAL
V
CC
V
CC
V
CC
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
GND
CLK
D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
R8, 1.2k
D8
R9, 1.2k
D9
R10, 1.2k
D10
R11, 1.2k
D11
R12, 1.2k
D12
R13, 1.2k
D13
R14, 1.2k
D14
R15, 1.2k
R0, 1.2k
D0
R1, 1.2k
D1
R2, 1.2k
D2
R3, 1.2k
D3
R4, 1.2k
D4
R5, 1.2k
D5
R6, 1.2k
D6
R7, 1.2k
D7
JP2
LED
ENABLE
1011
U4E
74HC04
81
2
9
EXT_CLK
J1
1
2
A
IN
J2
R17
51
U4D
74HC04
R18
200Ω
1%
Figure 15. LTC1605-1 Suggested Evaluation Circuit Schematic

LTC1605-1CG#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 100ksps 16-Bit ADC 0V to 4V
Lifecycle:
New from this manufacturer.
Delivery:
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