Conversion Guide: P33 130nm to 65nm
Application Note Sep 2008
16 Order Number: 320005-04
5.7 Performance Improvements in P33 65nm
The write performance can be increased on P33 65nm by using the 1024 Byte/512
Word buffer. If buffered programming is being done using the 16 word buffer (similar to
130nm devices), no software changes need to be implemented.
To achieve maximum performance using the 1024 Byte/ 512 Word buffer on 65nm
devices, the following considerations apply during software modifications:
1. Use the Full 1024 Byte/ 512 Word Buffer
2. If 1024 Byte/ 512 Word Buffer is being used, the programming addresses should be
aligned in 512 word address boundaries. For example: Start Programming address is
000000h and End Programming Address is 0001FFh. Please refer to Figure 3.
3. If the addresses must be mis-aligned, they must be in chunks of 256 Words. For
example: Start Programming Address to Start Programming Address + 0000FFh (256
Words). Please refer to Figure 3.
The Read performance can be improved by providing read page buffer up to 16 Words
(P+1Dh).
Table 11: Value Changes
Num Difference
130nm 65nm
offset value offset Values
1 “n” such that typical max. buffer write time-out = 2
n
µ-sec 20h 512 20h 1024
2 “n” such that maximum buffer write time-out = 2
n
times typical 24h 1024 24h 4096
3 “n” such that maximum number of bytes in write buffer = 2
n
2Ah 64 2Ah 1024
4
Page Mode Read capability
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.
(P+1D)h 8 (P+1D)h 32
Figure 5: Main Array Representation
256
Words
000000h
000200h
0003FFh
Main Array Representation
512
Words
512
Words
256
Word s
0001FFh
256
Word s
256
Word s
FFFFFFh
