AOZ1253
Page 6 of 6 Rev. 1.1 March 2012
www.aosmd.com
Detailed Description
The AOZ1253 is a high efficiency current-mode buck
regulator with integrated both high-side and low-side
NMOS switches. It has a wide operating input voltage
range of 4.5V to 26V and can supply up to 3A of output
load current. AOZ1253’s key protection features include
input under voltage lockout, output over voltage
protection, cycle by cycle current limit, fault short
protection and thermal shut down. The AOZ1253 is
available in the exposed pad SO-8 package.
Soft Start
AOZ1253 starts a soft start that can be adjusted by an
external capacitor. The internal 2.5µA current source
starts to charge the external capacitor through the soft-
start pin. When soft-start voltage is higher than internal
enable threshold voltage, the IC starts to switch with
minimum on-time. With the soft-start voltage further
increasing, the IC starts to switch with wider on-time,
which drives the output (FB) following the soft-start
voltage until output reaches the pre-set value. The
output soft-start time can be calculated by:
SS
SS
SS
I
C
T 6.0
Light Load and PWM Operation
Under low output current settings, AOZ1253 will
operate in light load mode to obtain high efficiency. The
two modes of operation, PFM and PWM are determined
by the peak inductor current level and the output
feedback voltage. For very low output current and
consequently low peak inductor current, AOZ1253 will
operate under critical inductor current mode if FB
voltage is lower than threshold of V
H_PFM
. V
H_PFM
is
10mV higher than normal voltage reference. If output is
higher than that value, IC will turn-off to keep high light
load efficiency. As the output current increases, the IC
will leave PFM mode and will enter PWM mode
operating in fixed frequency continuous conduction
mode (CCM). In CCM mode, AOZ1253 operates with
the low side MOSFET switching in synchronous
rectification to obtain high efficiency performance.
Error Amplifier
AOZ1253 uses an error amplifier that has a
transconductance of 1000µA/V. Closed loop stability is
realized through the frequency compensation network
connected between COMP to AGND. (Refer to Loop
Compensation)
Slope Compensation
A slope compensation ramp is also added in the control
loop design to prevent sub harmonic oscillations. There
is sufficient inductor current information to obtain stabile
current mode operation. The output voltage is divided
by the resistive voltage divider at the FB pin. The
internal transconductance error amplifier then amplifies
the difference between the voltages at FB with the
reference voltage. The error signal voltage is an input to
the COMP and is compared against the current signal
which consists of both the inductor current and slope
comp ramp at the PWM comparator input. If this current
signal is less than the error voltage the high side switch
will turn on.
Switching Frequency
The AOZ1253 has a fixed switching frequency under
PWM mode of operation through an internal oscillator.
Its nominal switching frequency is set to 600kHz.
Not Recommended For New Designs
