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AOZ1253PI

P1-P3P4-P6P7-P9P10-P12P13-P13
AOZ1253
Page 7 of 7 Rev. 1.1 March 2012
www.aosmd.com
Output Voltage Setting
The output voltage is set by a resistor divider network of
R
1
and R
2
, by feeding back the output to the FB pin.
The output setting is defined by:
2
1
16.0
R
R
V
O
Below Table 1 lists popular regulated outputs and the
corresponding values of R
1
, R
2
.
V
O
(V) R
1
(kΩ) R
2
(kΩ)
0.6 Open
1.0 6.67 10
1.5 15 10
1.8 20 10
2.5 31.7 10
3.3 45 10
5.0 73.3 10
Table 1.Output Voltage Setting
with Resistor Divider
The combination of R
1
and R
2
should be large enough
to avoid drawing excessive current from the output that
contributes to power loss. Since the switch duty cycle
can be as high as 100%, the maximum output voltage
can be set as high as the input voltage minus the
voltage drop of the high side NMOS and inductor .
Over Current Protection (OCP)
The primary signal used in over current protection is the
peak inductor. By employing peak current mode control,
the COMP voltage is proportional to the peak inductor
current. This voltage falls between the range of 0.4V
and 2.5V, increasing with output load current. AOZ1253
utilizes cycle by cycle current limit and limits the peak
inductor current. A preset current limit voltage is used
as a reference trip point. When the output current
exceeds the current limit range, the high side switch will
stop switching.
Under fault conditions where the output maybe shorted
to ground, V
OUT
will drop rapidly and AOZ1253’s
protection circuit will force the inductor current to decay
once the OCP level is reached within several switching
cycles. This feature helps to prevent catastrophic failure
and recovery of the IC once the short is removed.
AOZ1253 will initiate a soft start once the over-current
condition is removed.
Thermal Protection
An internal temperature sensor monitors the junction
temperature of the controller. The internal control circuit
shuts down the high-side NMOS once the junction
temperature exceeds 150ºC. The regulator has a 50°
hysteresis and will automatically restart when the
junction temperature decreases to 100ºC.
Input capacitor
The input bypass capacitor must be connected very
closely to the V
IN
and PGND pins of AOZ1253. This
mainly to ensure that proper filtering is maintained to
filter out the pulsing input current inherent to buck
regulator switching. The voltage rating of input
capacitor is selected to be higher than maximum input
voltage plus the input ripple voltage.
The input ripple voltage can be approximated by
equation below:
IN
O
IN
O
IN
O
IN
V
V
V
V
Cf
I
V
1
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
one key concern when selecting the capacitor. For a
buck regulator, the RMS value of input capacitor current
can be calculated by:
IN
O
IN
O
ORMSCIN
V
V
V
V
II 1
_
m equals the conversion ratio:
m
V
V
IN
O
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 1 below. It can be seen that when V
O
is
half of V
IN
, C
IN
is under the worst current stress. The
worst current stress on C
IN
is 0.5·I
O
.
Figure 1. I
CIN
vs. Voltage Conversion Ratio
Not Recommended For New Designs
AOZ1253
Page 8 of 8 Rev. 1.1 March 2012
www.aosmd.com
To ensure reliable operation, the input capacitors must
be selected to have a current rating higher than I
CIN-RMS
at the worst operating conditions. Ceramic capacitors
are preferred for input capacitors because of their low
ESR and high current rating. Depending on the
application circuits, other low ESR tantalum capacitor
may also be used. When selecting ceramic capacitors,
X5R or X7R type dielectric ceramic capacitors should
be used for their better temperature and voltage
characteristics. Note that the ripple current rating from
capacitor manufactures is based on certain amount of
life time. Further de-rating may be necessary in
practical design.
Inductor
The inductor is used to supply constant current to
output when it is driven by a switching voltage. For
given input and output voltage, inductance and
switching frequency together decide the inductor ripple
current, which is:
IN
OO
L
V
V
Lf
V
I 1
The peak inductor current is:
2
L
OLpeak
I
II
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 20% to
30% of output current.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor needs to be checked
for thermal and efficiency requirements.
Surface mount inductors in different shape and styles
are available from Coilcraft, Elytone and Murata.
Shielded inductors are small and radiate less EMI
noise. But they cost more than unshielded inductors.
The choice depends on EMI requirement, price and
size.
Output Capacitor
The output capacitor is selected based on the DC
output voltage rating, output ripple voltage specification
and ripple current rating. The selected output capacitor
must have a higher rated voltage specification than the
maximum desired output voltage including ripple. De-
rating needs to be considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
O
COLO
Cf
ESRIV
8
1
where,
C
O
is output capacitor value and
ESR
CO
is the Equivalent Series Resistor of output
capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the
switching frequency dominates. Output ripple is mainly
caused by capacitor value and inductor ripple current.
The output ripple voltage calculation can be simplified
to:
O
LO
Cf
IV
8
1
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided
by capacitor ESR and inductor ripple current. The
output ripple voltage calculation can be further
simplified to:
COLO
ESRIV
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric
type of ceramic, or other low ESR tantalum are
recommended to be used as output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It
can be calculated by:
12
_
L
RMSCO
I
I
Usually, the ripple current rating of the output capacitor
is a smaller issue because of the low current stress.
When the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
Not Recommended For New Designs
AOZ1253
Page 9 of 9 Rev. 1.1 March 2012
www.aosmd.com
Loop Compensation
The AOZ1253 employs peak current mode control for
ease-of-use and fast transient response. Peak current
mode control eliminates the double pole effect of the
output L&C filter. It greatly simplifies the compensation
loop design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
LO
p
RC
f
2
1
1
The zero is an ESR zero due to output capacitor and
it’s ESR. It is can be calculated by:
COO
Z
ESRC
f
2
1
1
where,
C
O
is the output filter capacitor;
R
L
is load resistor value; and
ESR
CO
is the equivalent series resistance of output
capacitor.
The compensation design is actually to shape the
converter control loop transfer function to get desired
gain and phase. Several different types of
compensation network can be used for the AOZ1253.
For most cases, a series capacitor and resistor network
connected to the COMP pin sets the pole-zero and is
adequate for a stable high-bandwidth control loop.
In the AOZ1253, FB pin and COMP pin are the
inverting input and the output of internal error amplifier.
A series R and C compensation network connected to
COMP provides one pole and one zero. The pole is:
VEAC
EA
p
GC
G
f
2
2
where,
G
EA
is the error amplifier transconductance, which is
1000·10
-6
A/V;
G
VEA
is the error amplifier voltage gain, which is 500
V/V; and
C
C
is compensation capacitor in the Typical Application
schematic on the first page.
The zero given by the external compensation network,
capacitor C
C
and resistor R
C
is located at:
CC
Z
RC
f
2
1
2
To design the compensation circuit, a target crossover
frequency f
C
for close loop must be selected. The
system crossover frequency is where control loop has
unity gain. The crossover is the also called the
converter bandwidth. Generally a higher bandwidth
means faster response to load transient. However, the
bandwidth should not be too high because of system
stability concern. When designing the compensation
loop, converter stability under all line and load condition
must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. It is
recommended to choose a crossover frequency equal
or less than 60kHz.
The strategy for choosing R
C
and C
C
is to set the cross
over frequency with R
C
and set the compensator zero
with C
C
. Using selected crossover frequency, f
C
, to
calculate R
C
:
CSEA
O
FB
O
CC
GG
C
V
V
fR
2
where,
f
C
is desired crossover frequency. For best
performance, f
C
is set to be about 1/10 of switching
frequency;
V
FB
is 0.6V;
G
EA
is the error amplifier transconductance, which is
1000·10
-6
A/V; and
G
CS
is the current sense circuit transconductance,
which is 4 A/V.
The compensation capacitor C
C
and resistor R
C
together make a zero. This zero is put somewhere
close to the dominate pole f
p1
but lower than 1/5 of
selected crossover frequency. C
C
can is selected by:
1
2
5.1
pC
C
FR
C
Equation above can also be simplified to:
C
LO
C
R
RC
C
Not Recommended For New Designs
P1-P3P4-P6P7-P9P10-P12P13-P13

AOZ1253PI

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IC REG BUCK ADJUSTABLE 3A 8SO
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