OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ATF-33143-BLKG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
ATF-33143
Low Noise Pseudomorphic HEMT
in a Surface Mount Plastic Package
Data Sheet
Features
Lead-free Option Available
Low Noise Figure
Excellent Uniformity in Product Speci cations
1600 micron Gate Width
Low Cost Surface Mount Small Plastic Package
SOT-343 (4 lead SC-70)
Tape-and-Reel Packaging Option Available
Speci cations
1.9 GHz; 4V, 80 mA (Typ.)
0.5 dB Noise Figure
15 dB Associated Gain
22 dBm Output Power at 1 dB Gain Compression
33.5 dBm Output 3
rd
Order Intercept
Applications
Tower Mounted Ampli er, Low Noise Ampli er and
Driver Ampli er for GSM/TDMA/CDMA Base Stations
LNA for Wireless LAN, WLL/RLL and MMDS
Applications
General Purpose Discrete PHEMT for other Ultra Low
Noise Applications
Description
Avago’s ATF-33143 is a high dynamic range, low noise
PHEMT housed in a 4-lead SC-70 (SOT-343) surface mount
plastic package.
Based on its featured performance, ATF-33143 is ideal for
the  rst or second stage of base station LNA due to the
excellent combination of low noise  gure and enhanced
linearity
[1]
. The device is also suitable for applications in
Wireless LAN, WLL/RLL, MMDS, and other systems requiring
super low noise  gure with good intercept in the 450 MHz
to 10 GHz frequency range.
Note:
1. From the same PHEMT FET family, the smaller geometry ATF-
34143 may also be considered for the higher gain performance,
particularly in the higher frequency band (1.8 GHz and up).
Surface Mount Package SOT-343
Pin Connections and Package Marking
Note:
Top View. Package marking provides
orientation and identi cation.
“3P” = Device code
“x” = Date code character. A new character
is assigned for each month, year.
SOURCE
DRAIN
GATE
SOURCE
3Px
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model (Class A)
ESD Human Body Model (Class 0)
Refer to Avago Application Note A004R:
Electrostatic Discharge Damage and Control.
2
ATF-33143 Absolute Maximum Ratings
[1]
Absolute
Symbol Parameter Units Maximum
V
DS
Drain - Source Voltage
[2]
V 5.5
V
GS
Gate - Source Voltage
[2]
V -5
V
GD
Gate Drain Voltage
[2]
V -5
I
DS
Drain Current
[2]
mA I
dss
[3]
P
diss
Total Power Dissipation
[4]
mW 600
P
in max
RF Input Power dBm 20
T
CH
Channel Temperature
[5]
°C 160
T
STG
Storage Temperature °C -65 to 160
jc
Thermal Resistance
[6]
°C/W 145
Notes:
1. Operation of this device above any one of
these parameters may cause permanent
damage.
2. Assumes DC quiesent conditions.
3. V
GS
= 0V
4. Source lead temperature is 25°C. Derate
6 mW/°C for T
L
> 60°C.
5. Please refer to failure rates in reliability
section to assess the reliability impact
of running devices above a channel
temperature of 140°C.
6. Thermal resistance measured using 150°C
Liquid Crystal Measurement method.
Product Consistency Distribution Charts
[8, 9]
Notes:
7. Under large signal conditions, V
GS
may swing positive and the drain current may exceed I
dss
. These conditions are acceptable as long as the maximum
P
diss
and P
in max
ratings are not exceeded.
8. Distribution data sample size is 450 samples taken from 9 di erent wafers. Future wafers allocated to this product may have nominal values
anywhere within the upper and lower spec limits.
9.
Measurements made on production test board. This circuit represents a trade-o between an optimal noise match and a realizeable match based
on production test requirements. Circuit losses have been de-embedded from actual measurements.
10. The probability of a parameter being between ±1 is 68.3%, between ±2σ is 95.4% and between ±3σ is 99.7%.
V
DS
(V)
Figure 1. Typical Pulsed I-V Curves
[7]
. (V
GS
= -0.2 V per step)
I
DS
(mA)
02 4 68
500
400
300
200
100
0
0 V
–0.6 V
+0.6 V
NF (dB)
Figure 2. NF @ 2 GHz, 4 V, 80 mA.
LSL=0.2, Nominal=0.53, USL=0.8
0.2 0.40.3 0.60.5 0.80.7
-3 Std
+3 Std
Cpk = 1.7
Std = 0.05
120
100
80
60
40
20
0
OIP3 (dBm)
Figure 3. OIP3 @ 2 GHz, 4 V, 80 mA.
LSL=30.0, Nominal=33.3, USL=37.0
29 37
-3 Std +3 Std
Cpk = 1.21
Std = 0.94
100
80
60
40
20
0
3331 35
GAIN (dB)
Figure 4. Gain @ 2 GHz, 4 V, 80 mA.
LSL=13.5, Nominal=14.8, USL=16.5
13 14 15 16 17
-3 Std +3 Std
Cpk = 2.3
Std = 0.2
120
100
80
60
40
20
0
3
Figure 5. Block diagram of 2 GHz production test board used for Noise Figure, Associated Gain, P1dB, and OIP3 measurements. This circuit represents a
trade-o between an optimal noise match and a realizable match based on production test requirements. Circuit losses have been de-embedded from
actual measurements.
Input
50 Ohm
Transmission
Line Including
Gate Bias T
(0.5 dB loss)
Input
Matching Circuit
G_mag = 0.20
G_ang = 124
(0.3 dB loss)
DUT
50 Ohm
Transmission
Line Including
Drain Bias T
(0.5 dB loss)
Output
ATF-33143 DC Electrical Speci cations T
A
= 25°C, RF parameters measured in a test circuit for a typical device
Symbol Parameters and Test Conditions Units Min. Typ.
[2]
Max.
I
dss
[1]
Saturated Drain Current V
DS
= 1.5 V, V
GS
= 0 V mA 175 237 305
V
P
[1]
Pincho Voltage V
DS
= 1.5 V, I
DS
= 10% of I
dss
V -0.65 -0.5 -0.35
I
d
Quiescent Bias Current V
GS
= -0.5 V, V
DS
= 4 V mA — 80 —
g
m
[1]
Transconductance V
DS
= 1.5 V, g
m
= I
dss
/V
P
mmho 360 440 —
I
GDO
Gate to Drain Leakage Current V
GD
= 5 V μA 1000
I
gss
Gate Leakage Current V
GD
= V
GS
= -4 V μA — 42 600
f = 2 GHz V
DS
= 4 V, I
DS
= 80 mA dB 0.5 0.8
NF
Noise Figure
V
DS
= 4 V, I
DS
= 60 mA 0.5
f = 900 MHz V
DS
= 4 V, I
DS
= 80 mA dB 0.4
V
DS
= 4 V, I
DS
= 60 mA 0.4
f = 2 GHz V
DS
= 4 V, I
DS
= 80 mA dB 13.5 15 16.5
G
a
Associated Gain
[3]
V
DS
= 4 V, I
DS
= 60 mA 15
f = 900 MHz V
DS
= 4 V, I
DS
= 80 mA dB 21
V
DS
= 4 V, I
DS
= 60 mA 21
Output 3
rd
Order
f = 2 GHz V
DS
= 4 V, I
DS
= 80 mA dBm 30 33.5
OIP3
Intercept Point
[3]
5 dBm Pout/Tone V
DS
= 4 V, I
DS
= 60 mA 32
f = 900 MHz V
DS
= 4 V, I
DS
= 80 mA dBm 32.5
5 dBm Pout/Tone V
DS
= 4 V, I
DS
= 60 mA 31
1 dB Compressed
f = 2 GHz V
DS
= 4 V, I
DS
= 80 mA dBm 22
P
1dB
Compressed Power
[3]
V
DS
= 4 V, I
DS
= 60 mA 21
f = 900 MHz V
DS
= 4 V, I
DS
= 80 mA dBm 21
V
DS
= 4 V, I
DS
= 60 mA 20
Notes:
1. Guaranteed at wafer probe level.
2. Typical value determined from a sample size of 450 parts from 9 wafers.
3. Measurements obtained using production test board described in Figure 5.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ATF-33143-BLKG

Mfr. #:
Buy ATF-33143-BLKG
Manufacturer:
Broadcom / Avago
Description:
RF JFET Transistors Transistor GaAs Low Noise
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet