PS030603-1013 5
eZ80Acclaim!
™
/eZ80AcclaimPlus!
™
Ethernet Modules
Product Specification
All signals with an overline are active Low. For example, B/W, in which WORD is active
Low, and B/W, in which BYTE is active Low.
Table 1. eZ80Acclaim!
™
/eZ80AcclaimPlus!
™
Ethernet Module Peripheral Bus:
Connector Pin Identification
Pin No Symbol
Pull Up/
Down Signal Direction Comments
1 Reserved
2 Reserved
3 Reserved
4 Reserved
5TRSTN
Input Reset for on-chip instrumentation (OCI).
6 Reserved
7 F91_WE
PU 10 kΩ Input A Low enables a write to on-chip Flash
memory. If this pin is unconnected, on-chip
Flash memory is write-protected.
8 Reserved
9GND V
SS
/Ground (0 V).
10 V
CC
3.3 V supply input pin.
11 A6 Bidirectional
12 A0 Bidirectional
13 A10 Bidirectional
14 A3 Bidirectional
15 GND V
SS
/Ground (0 V).
16 V
CC
3.3 V supply input pin.
17 A8 Bidirectional
18 A7 Bidirectional
19 A13 Bidirectional
20 A9 Bidirectional
21 A15 Bidirectional
22 A14 Bidirectional
Notes:
1. External capacitive loads on RD
, WR, IORQ, MREQ, D0–D7, and A0–A23 must be below 10 pF to satisfy timing
requirements for the CPU.
2. All unused inputs must be pulled to either V
DD
or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
3. All inputs are CMOS level 3.3 V (5 V-tolerant), except where otherwise noted.
