PS030603-1013 11
eZ80Acclaim!
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/eZ80AcclaimPlus!
™
Ethernet Modules
Product Specification
51 CS3 Output Used on the eZ80190, eZ80L92, eZ80F92,
eZ80F93 devices and connected to the CS8900
EMAC.
52 DIS_IRDA
PU 10 kΩ Input A Low disables the onboard IRDA transceiver to
use PC0/PC1 UART pins externally.
53 RESET PU 2 kΩ Bidirectional Reset Output from module or push-button reset.
54 WAIT PU 2 kΩ Input Driving the WAIT
pin Low forces the CPU to
provide additional clock cycles for an external
peripheral or external memory to complete its read
or write operation.
55 V
CC
3.3 V supply input pin.
56 GND V
SS
/Ground (0 V).
57 HALT_SLP Output, Active
Low
A Low on this pin indicates that the CPU enters
either HALT or SLEEP Mode because of execution
of either a HALT or SLP instruction.
58 NMI PU 10 kΩ Schmitt-trigger
Input, Active Low
The NMI
input is a higher priority input than the
maskable interrupts. It is always recognized at the
end of an instruction, regardless of the state of the
interrupt enable control bits. This input includes a
Schmitt-trigger to allow RC rise times. This
external NMI
signal is combined with an internal
NMI
signal generated from the WDT block before
being connected to the NMI
input of the CPU.
59 V
CC
3.3 V supply input pin.
60 Reserved NC Reserved; no connection.
Table 2. eZ80Acclaim!
™
/eZ80AcclaimPlus!
™
Ethernet Module Input/Output Connector:
Pin Identification (Continued)
Pin No Symbol
Pull Up/
Down Signal Direction Comments
Notes:
1. External capacitive loads on RD
, WR, IORQ, MREQ, D0–D7, and A0–A23 must be below 10 pF to satisfy timing
requirements for the CPU.
2. All unused inputs must be pulled to either V
DD
or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
3. All inputs are CMOS level 3.3 V (5 V-tolerant), except where otherwise noted.
