PS030603-1013 7
eZ80Acclaim!
™
/eZ80AcclaimPlus!
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Ethernet Modules
Product Specification
Input/Output Connector
Figure 3 presents a pin layout of the 60-pin I/O connector (J2) of the modules. However,
the eZ80
®
Development Platform features a 50-pin connector. eZ80Acclaim!
™
/
eZ80AcclaimPlus!
™
Ethernet Modules are designed to interface pin 60 of their J2 connec-
tors to pin 50 of the eZ80 Development Platform’s JP2 connector so that pins 1–10 of the
Modules overlap the edge of the eZ80 development platform. Table 2 describes the pins.
49 D5 PU 4 kΩ Bidirectional
50 GND V
SS
/Ground (0 V).
51 D7 PU 4 kΩ Bidirectional
52 D6 Bidirectional
53 MREQ
Bidirectional
54 IORQ
Bidirectional
55 GND V
SS
/Ground (0 V).
56 RD
Bidirectional
57 WR
Bidirectional
58 INSTRD
Output
59 BUSACK
Output
60 BUSREQ
PU 2 kΩ Input
Table 1. eZ80Acclaim!
™
/eZ80AcclaimPlus!
™
Ethernet Module Peripheral Bus:
Connector Pin Identification (Continued)
Pin No Symbol
Pull Up/
Down Signal Direction Comments
Notes:
1. External capacitive loads on RD, WR, IORQ, MREQ, D0–D7, and A0–A23 must be below 10 pF to satisfy timing
requirements for the CPU.
2. All unused inputs must be pulled to either V
DD
or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
3. All inputs are CMOS level 3.3 V (5 V-tolerant), except where otherwise noted.
