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NCP6153MNTWG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
NCP6153
http://onsemi.com
16
Table 1. VR12 VID CODES
VID7 HEXVoltage (V)VID0VID1VID2VID3VID4VID5VID6
1 1 0 1 0 1 1 1 1.32000 D7
1 1 0 1 1 0 0 0 1.32500 D8
1 1 0 1 1 0 0 1 1.33000 D9
1 1 0 1 1 0 1 0 1.33500 DA
1 1 0 1 1 0 1 1 1.34000 DB
1 1 0 1 1 1 0 0 1.34500 DC
1 1 0 1 1 1 0 1 1.35000 DD
1 1 0 1 1 1 1 0 1.35500 DE
1 1 0 1 1 1 1 1 1.36000 DF
1 1 1 0 0 0 0 0 1.36500 E0
1 1 1 0 0 0 0 1 1.37000 E1
1 1 1 0 0 0 1 0 1.37500 E2
1 1 1 0 0 0 1 1 1.38000 E3
1 1 1 0 0 1 0 0 1.38500 E4
1 1 1 0 0 1 0 1 1.39000 E5
1 1 1 0 0 1 1 0 1.39500 E6
1 1 1 0 0 1 1 1 1.40000 E7
1 1 1 0 1 0 0 0 1.40500 E8
1 1 1 0 1 0 0 1 1.41000 E9
1 1 1 0 1 0 1 0 1.41500 EA
1 1 1 0 1 0 1 1 1.42000 EB
1 1 1 0 1 1 0 0 1.42500 EC
1 1 1 0 1 1 0 1 1.43000 ED
1 1 1 0 1 1 1 0 1.43500 EE
1 1 1 0 1 1 1 1 1.44000 EF
1 1 1 1 0 0 0 0 1.44500 F0
1 1 1 1 0 0 0 1 1.45000 F1
1 1 1 1 0 0 1 0 1.45500 F2
1 1 1 1 0 0 1 1 1.46000 F3
1 1 1 1 0 1 0 0 1.46500 F4
1 1 1 1 0 1 0 1 1.47000 F5
1 1 1 1 0 1 1 0 1.47500 F6
1 1 1 1 0 1 1 1 1.48000 F7
1 1 1 1 1 0 0 0 1.48500 F8
1 1 1 1 1 0 0 1 1.49000 F9
1 1 1 1 1 0 1 0 1.49500 FA
1 1 1 1 1 0 1 1 1.50000 FB
1 1 1 1 1 1 0 0 1.50500 FC
1 1 1 1 1 1 0 1 1.51000 FD
1 1 1 1 1 1 1 0 1.51500 FE
1 1 1 1 1 1 1 1 1.52000 FF
NCP6153
http://onsemi.com
17
VR12_EN
SCLK
SDIO VSPA VID PKT
VSPA
SVID bus idle
VSP VID pkt
VSP
SVID Alert
VR_RDYA
VR_RDY
Status PKT
12V
5V
Figure 4. Start Up Timing Diagram
SCLK
SDIO
VR latch
CPU
send
SCLK
SDIO
CPU latch
VR
send
VR Driving, Single Data Rate
Figure 5. SVID Timing Diagram
CPU Driving, Single Data Rate
t
hld
T
CO_CPU
T
CO_CPU
t
su
T
co_CPU
= clock to data delay in CPU
t
su
= 0.5 * T − T
co_CPU
t
hld
= 0.5 * T + T
co_CPU
T
co_VR
= clock to data delay in VR
t
su
= T − 2 * T
fly
− T
co_VR
t
hld
= 2 * T
fly
+ T
co_VR
T
fly
propagation time on Serial VID bus
t
su
t
hld
T
CO_VR
NCP6153
http://onsemi.com
18
Table 2. STATE TRUTH TABLE
STATE VR_RDY(A) Pin
Error AMP
Comp(A) Pin
OVP(A) and
UVP(A)
DRVON Pin Method of Reset
POR
0 < V
CC
< UVLO
N/A N/A N/A Resistive pull down
Disabled
EN < threshold
UVLO > threshold
Low Low Disabled Low
Start up Delay &
Calibration
EN > threshold
UVLO > threshold
Low Low Disabled Low
DRVON Fault
EN > threshold
UVLO > threshold
DRVON < threshold
Low Low Disabled Resistive pull up Driver must release
DRVON to high
Soft Start
EN > threshold
UVLO > threshold
DRVON > High
Low Operational Active / No
latch
High
Normal Operation
EN > threshold
UVLO > threshold
DRVON > High
High Operational Active /
Latching
High N/A
Over Voltage Low N/A DAC +
150 mV
High
Over Current Low Operational Last DAC
Code
Low
VID Code = 00h Low: if Reg34h:bit0 = 0;
High: if Reg34h:bit0 = 1
Clamped at
0.9 V
Disabled High, PWM outputs
in low state
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

NCP6153MNTWG

Mfr. #:
Buy NCP6153MNTWG
Manufacturer:
ON Semiconductor
Description:
Switching Controllers DUAL OUTPUT Cntrllr
Lifecycle:
New from this manufacturer.
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