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NCP6153MNTWG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
NCP6153
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NCP6153 QFN52 SINGLE ROW PIN DESCRIPTIONS
Pin
No.
DescriptionSymbol
17 DIFFOUTA Output of the aux differential remote sense amplifier
18 TRBSTA Compensation pin for aux rail load transient boost
19 COMPA Output of the aux error amplifier and the inverting input of the PWM comparator for aux output
20 ILIMA Over current shutdown threshold setting for aux output. A resistor to CSCOMPA sets the threshold
21 DROOPA Used to program droop function for aux output. It s connected to the resistor divider placed between
CSCOMPA and CSREFA
22 CSCOMPA Output of total current sense amplifier for aux output
23 IOUTA Total output current monitor for aux output
24 CSSUMA Inverting input of total current sense amplifier for aux output
25 CSPA Non−Inverting input to aux current sense amplifier
26 CSNA Inverting input to aux current sense amplifier
27 VBOOTA VBOOTA Voltage input pin. Set to adjust the aux boot−up voltage
28 PWMA/IMAXA Aux PWM output to gate driver. Also as ICC_MAXA input pin for aux rail. During start up it is used to
program ICC_MAXA with a resistor to ground
29 PWM4 Phase 4 PWM output. Pull to Vcc will configure as 3−phase operation
30 PWM2/VBOOT Phase 2 PWM output. Also as VBOOT input pin to adjust the core rail boot−up voltage. During start up it
is used to program VBOOT with a resistor to ground
31 PWM3/IMAX Phase 3 PWM output. Also as ICC_MAX Input Pin for core rail. During start up it is used to program
ICC_MAX with a resistor to ground
32 PWM1/ADDR Phase 1 PWM output. Also as Address program pin. A resistor to ground on this pin programs the SVID
address of the device
33 DRON Bidirectional gate drive enable for core output
34 CSP1 Non−inverting input to current balance sense amplifier for phase 1
35 CSN1 Inverting input to current balance sense amplifier for phase 1
36 CSP3 Non−inverting input to current balance sense amplifier for phase 3
37 CSN3 Inverting input to current balance sense amplifier for phase 3
38 CSP2 Non−inverting input to current balance sense amplifier for phase 2
39 CSN2 Inverting input to current balance sense amplifier for phase 2
40 CSN4 Inverting input to current balance sense amplifier
41 CSP4 Non−inverting input to current balance sense amplifier for phase 4
42 CSREF Total output current sense amplifier reference voltage input
43 IOUT Total output current monitor for core output.
44 CSSUM Inverting input of total current sense amplifier for core output
45 CSCOMP Output of total current sense amplifier for core output
46 DROOP Used to program droop function for core output. It’s connected to the resistor divider placed between
CSCOMP and CSREF summing node
47 ILIM Over current shutdown threshold setting for core output. Resistor to CSCOMP to set threshold
48 COMP Output of the error amplifier and the inverting inputs of the PWM comparators for the core output
49 FB Error amplifier voltage feedback for core output
50 TRBST Compensation pin for core rail load transient boost.
51 VSN Inverting input to the core differential remote sense amplifier
52 DIFFOUT Output of the core differential remote sense amplifier
53 FLAG / GND Power supply return (QFN Flag)
NCP6153
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NCP6153 APPLICATION CONTROL CIRCUIT (TYPICAL)
Figure 3. NCP6153 VCCP and GT Regulator
NCP6153
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6
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL INFORMATION
Pin Symbol V
MAX
V
MIN
COMP, COMPA V
CC
+ 0.3 V −0.3 V
CSCOMP, CSCOMPA V
CC
+ 0.3 V −0.3 V
VSN GND + 300 mV GND – 300 mV
DIFFOUT, DIFFOUTA V
CC
+ 0.3 V −0.3 V
VR_RDY, VR_RDYA V
CC
+ 0.3 V −0.3 V
VCC 6.5 V −0.3 V
ROSC V
CC
+ 0.3 V −0.3 V
IOUT, IOUTA Output 2.0 V −0.3 V
VRMP +25 V −0.3 V
All Other Pins V
CC
+ 0.3 V −0.3 V
*All signals referenced to GND unless noted otherwise.
THERMAL INFORMATION
Description Symbol Typ Unit
Thermal Characteristic − QFN Package (Note 1)
R
q
JA
68 °C/W
Operating Junction Temperature Range (Note 2) T
J
−10 to 125 °C
Operating Ambient Temperature Range −10 to 100 °C
Maximum Storage Temperature Range T
STG
−40 to +150 °C
Moisture Sensitivity Level − QFN Package MSL 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
NCP6153 ELECTRICAL CHARACTERISTICS Unless otherwise stated: −10°C < T
A
< 100°C; V
CC
= 5 V; C
VCC
= 0.1 mF
Parameter Test Conditions Min Typ Max Unit
ERROR AMPLIFIER
Input Bias Current @ 1.3 V −400 400 nA
Open Loop DC Gain C
L
= 20 pF to GND,
R
L
= 10 kW to GND
80 dB
Open Loop Unity Gain Bandwidth C
L
= 20 pF to GND,
R
L
= 10 kW to GND
50 MHz
Slew Rate
DV
in
= 100 mV, G = −10 V/V,
DV
out
= 1.5 V – 2.5 V,
C
L
= 20 pF to GND,
DC Load = 10 k to GND
20
V/ms
Maximum Output Voltage I
SOURCE
= 2.0 mA 3.5 − − V
Minimum Output Voltage I
SINK
= 2.0 mA − − 1 V
DIFFERENTIAL SUMMING AMPLIFIER
Input Bias Current VSP, VSPA ,VSN, VSNA = 1.3 V −400 − 400 nA
VSP Input Voltage Range −0.3 − 3.0 V
VSN Input Voltage Range −0.3 − 0.3 V
3. Guaranteed by design or characterization data, not in production test.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

NCP6153MNTWG

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Manufacturer:
ON Semiconductor
Description:
Switching Controllers DUAL OUTPUT Cntrllr
Lifecycle:
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