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Controller
POR
Disable
VCC > UVLO
Calibrate
Drive Off
Phase
Detect
Soft Start
Ramp
Normal
VR_RDY
OVP
UVP
EN = 1
3.5 ms and CAL DONE
VCCP > UVLO and DRON HIGH
EN = 0
VS > OVP
VDRP > ILIM
NO_CPU
INVALID VID
VS < UVP
VS > UVP
DAC = VID
VCC < UVLO
DAC = Vboot
Figure 6. State Diagram
Soft Start
Ramp
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General
The NCP6153 is a dual output four/three phase plus one phase dual edge modulated multiphase PWM controller designed
to meet the Intel VR12 specifications with a serial SVID control interface. The NCP6153 implements PS0, PS1, PS2 and PS3
power saving states. It is designed to work in notebook, desktop, and server applications.
For Core Rail:
Power Status PWM Output Operating Mode
PS0 Multiphase PWM interleaving output
PS1 Singlephase RPM CCM mode (PWM1 only, PWM2~4 stay in Mid)
PS2 Singlephase RPM DCM mode (PWM1 only, PWM2~4 stay in Mid)
PS3 Singlephase RPM DCM mode (PWM1 only, PWM2~4 stay in Mid)
For AUX Rail:
Power Status PWM Output Operating Mode
PS0 PWM interleaving with Core Rail / RPM CCM mode
PS1 PWM interleaving with Core Rail / RPM CCM mode
PS2 RPM DCM mode
PS3 RPM DCM mode
VID code change is supported by SVID interface with three options as below:
Option
SVID Command
Code
Feature
Register Address
(Indicating the slew rate of VID code change)
SetVID_Fast 01h
> 10 mV/ms VID code change
slew rate
24h
SetVID_Slow 02h = 1/4 of SetVID_Fast VID
code change slew rate
25h
SetVID_Decay 03h No control, VID code down N/A
Serial VID
The NCP6153 supports the Intel serial VID interface. It communicates with the microprocessor through three wires (SCLK,
SDIO, ALERT#). The table of supported registers is shown below.
Index Name Description Access Default
00h Vendor ID Uniquely identifies the VR vendor. The vendor ID assigned by Intel to
ON Semiconductor is 0x1Ah
R 0x1Ah
01h Product ID Uniquely identifies the VR product. The VR vendor assigns this number. R 0x51
02h Product
Revision
Uniquely identifies the revision or stepping of the VR control IC. The VR vendor as-
signs this data.
R 0x0A
05h Protocol ID Identifies the SVID Protocol the controller supports R 0x01
06h Capability Informs the Master of the controller’s Capabilities, 1 = supported, 0 = not supported
Bit 7 = Iout_format. Bit 7 = 0 when 1A = 1LSB of Reg 15h. Bit 7 = 1 when Reg 15 FFh
= Icc_Max. Default = 1
Bit 6 = ADC Measurement of Temp Supported = 1
Bit 5 = ADC Measurement of Pin Supported = 0
Bit 4 = ADC Measurement of Vin Supported = 0
Bit 3 = ADC Measurement of Iin Supported = 0
Bit 2 = ADC Measurement of Pout Supported = 1
Bit 1 = ADC Measurement of Vout Supported = 1
Bit 0 = ADC Measurement of Iout Supported = 1
R 0xC7
07h Generic ID 51h or 31h, depending on the generic R 51h or
31h
10h Status_1 Data register read after the ALERT# signal is asserted. Conveying the status of the VR. R 00h
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Index DefaultAccessDescriptionName
11h Status_2 Data register showing optional status_2 data. R 00h
12h Temp zone Data register showing temperature zones the system is operating in R 00h
15h I_out 8 bit binary word ADC of current. This register reads 0xFF when the output current is
at Icc_Max
R 01h
16h V_out 8 bit binary word ADC of output voltage, measured between VSP and VSN. LSB size
is 8 mV
R 01h
17h VR_Temp 8 bit binary word ADC of voltage. Binary format in deg C, IE 100C = 64h. A value of
00h indicates this function is not supported
R 01h
18h P_out 8 bit binary word representative of output power. The output voltage is multiplied by
the output current value and the result is stored in this register. A value of 00h indic-
ates this function is not supported
R 01h
1Ch Status 2
Last read
When the status 2 register is read its contents are copied into this register. The format
is the same as the Status 2 Register.
R 00h
21h Icc_Max Data register containing the Icc_Max the platform supports. The value is measured on
the ICCMAX pin on power up and placed in this register. From that point on the re-
gister is read only.
R 00h
22h Temp_Max Data register containing the max temperature the platform supports and the level VR_hot
asserts. This value defaults to 100°C and programmable over the SVID Interface
R/W 64h
24h SR_fast
Slew Rate for SetVID_fast commands. Binary format in mV/ms.
R 0Ah
25h SR_slow Slew Rate for SetVID_slow commands. It is 4X slower than the SR_fast rate. Binary
format in mV/ms
R 02h
26h Vboot The Vboot is programmed using resistors on the Vboot pin which is sensed on power
up. The controller will ramp to Vboot and hold at Vboot until it receives a new SVID
SetVID command to move to a different voltage.
R 00h
30h Vout_Max Programmed by master and sets the maximum VID the VR will support. If a higher
VID code is received, the VR should respond with “not supported” acknowledge. VR
12 VID format.
RW FBh
31h VID setting Data register containing currently programmed VID voltage. VID data format. RW 00h
32h Pwr State Register containing the current programmed power state. RW 00h
33h Offset Sets offset in VID steps added to the VID setting for voltage margining. Bit 7 is sign
bit, 0 = positive margin, 1= negative margin. Remaining 7 BITS are # VID steps for
margin 2s complement.
00h = no margin
01h = +1 VID step
02h = +2 VID steps
FFh = 1 VID step
FEh = 2 VID steps.
RW 00h
34h MultiVR
Config

NCP6153MNTWG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers DUAL OUTPUT Cntrllr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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