MAX8520/MAX8521
The output common-mode ripple voltage can be calcu-
lated as follows:
V
RIPPLEpk-pk
= LIR x I
TEC(MAX)
(ESR + 1/8 x C x fs)
A 1µF ceramic capacitor with ESR of 10 mΩ with LIR =
12% and I
TEC(MAX)
= 1.5A will result in V
RIPPLE(P-P)
of
24.3mV. For size-constraint application, the capacitor
can be made smaller at the expense of higher ripple
voltage. However, the capacitance must be high
enough so that the LC resonant frequency is less than
1/5 the switching frequency:
where f is the resonant frequency of the output filter.
Differential Mode Filter Capacitor
The differential-mode filter capacitor (C5 in Figure 1) is
used to bypass differential ripple current through the
TEC as the result of unequal duty cycle of each output.
This happens when the TEC current is not at zero. As
TEC current increases from zero, both outputs move
away from the 50% duty-cycle point complementarily.
The common-mode ripple decreases, but the differential
ripple does not cancel perfectly, and there will be a
resulting differential ripple. The maximum value happens
when one output is at 75% duty cycle and the other is at
25% duty cycle. At this operating point, the differential
ripple is equal to 1/2 of the maximum common-mode rip-
ple. The TEC ripple current determines the TEC perfor-
mance, because the maximum temperature differential
that can be created between the terminals of the TEC
depends on the ratio of ripple current and DC current.
The lower the ripple current, the closer to the ideal maxi-
mum. The differential-mode capacitor provides a low-
impedance path for the ripple current to flow, so that the
TEC ripple current is greatly reduced. The TEC ripple
current then can be calculated as follows:
I
TEC(RIPPLE)
= (0.5 x LIR x I
TEC(MAX)
) x (Z
C5
)/(R
TEC
+ R
SENSE
+ Z
C5
)
where Z
C5
is the impedance of C5 at twice the switching
frequency, R
TEC
is the TEC equivalent resistance, and
R
SENSE
is the current-sense resistor.
Decoupling Capacitor Selection
Decouple each power supply input (V
DD
, PVDD1,
PVDD2) with a 1µF ceramic capacitor close to the sup-
ply pins. In applications with long distances between
the source supply and the MAX8520/MAX8521, addi-
tional bypassing may be needed to stabilize the input
supply. In such cases, a low-ESR electrolytic or ceramic
capacitor of 100µF or more at V
DD
is sufficient.
Compensation Capacitor
A compensation capacitor is needed to ensure current-
control-loop stability (see Figure 3). Select the capacitor
so that the unity-gain bandwidth of the current-control
loop is less than or equal to 10% the resonant frequency
of the output filter:
where:
f
BW
= Unity-gain bandwidth frequency, less than or
equal to 10% the output filter resonant frequency
g
m
= Loop transconductance, typically 100µA/V
C
COMP
= Value of the compensation capacitor
R
TEC
= TEC series resistance, use the minimum resis-
tance value
R
SENSE
= Sense resistor
Setting Voltage and Current Limits
Certain TEC parameters must be considered to guarantee
a robust design. These include maximum positive current,
maximum negative current, and the maximum voltage
allowed across the TEC. These limits should be used to
set the MAXIP, MAXIN, and MAXV voltages.
Setting Max Positive and Negative TEC Current
MAXIP and MAXIN set the maximum positive and nega-
tive TEC currents, respectively. The default current limit
is ±150mV/R
SENSE
when MAXIP and MAXIN are con-
nected to REF. To set maximum limits other than the
defaults, connect a resistor-divider from REF to GND to
set V
MAXI_
. Use resistors in the 10kΩ to 100kΩ range.
V
MAXI_
is related to ITEC by the following equations:
V
MAXIP
= 10(I
TECP(MAX)
R
SENSE
)
V
MAXIN
= 10(I
TECN(MAX)
R
SENSE
)
where I
TECP(MAX)
is the maximum positive TEC current
and I
TECN(MAX)
is the negative maximum TEC current.
Positive TEC current occurs when CS is less than OS1:
I
TEC
x R
SENSE
= OS1 - CS
when I
TEC
> 0A.
I
TEC
R
SENSE
= CS - OS1
when I
TEC
< 0A.
