MAX8520/MAX8521
6) To ensure high DC-loop gain and minimum loop
error, keep the board layout adjacent to the negative
input pin of the integrator (U2 in Figure1) clean and free
of moisture. Any contamination or leakage current into
this node can act to lower the DC gain of the integrator
which can degrade the accuracy of the thermal loop. If
space is available, it can also be helpful to surround the
negative input node of the integrator with a grounded
guard ring.
Refer to the MAX8520/MAX8521 evaluation kit for a
PCB layout example.
Chip Information
PROCESS: BiCMOS
Smallest TEC Power Drivers for Optical
Modules
16 ______________________________________________________________________________________
Pin Configurations
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO.
LAND
PATTERN NO.
20 TQFN-EP T2055+4
21-0140
90-0009
6 x 6 UCSP B36-2
21-0082
Refer to Application Note 1891
36 WLP W363A3+2
21-0024
Refer to Application Note 1891
