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LT3580IDD#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
LT3580
4
3580fg
TYPICAL PERFORMANCE CHARACTERISTICS
Switch Current Limit at 1MHz Switch Saturation Voltage
Switch Current Limit at Minimum
Duty Cycle
Switch Current Limit at Minimum
Duty Cycle
Positive Feedback Voltage
Switching Waveforms for
Figure 14 Circuit
Oscillator Frequency
Oscillator Frequency During
Soft-Start
Internal UVLO
T
A
= 25°C unless otherwise specified
DUTY CYCLE (%)
10
0
SWITCH CURRENT LIMIT (A)
0.5
1.0
1.5
2.0
30 50
70
90
3580 G01
2.5
20 40
60
80
SWITCH CURRENT (A)
0
SATURATION VOLTAGE (mV)
200
250
300
2
3580 G02
150
100
0
0.5
1
1.5
50
400
350
SS VOLTAGE (mV)
0
0
SWITCH CURRENT (A)
0.5
1.0
1.5
2.0
200
400 600 800
3580 G03
1000 1200
2.5
TEMPERATURE (°C)
–50
0
SWITCH CURRENT LIMIT (A)
0.5
1.0
1.5
2.0
2.5
3.0
0 50 100
3580 G04
TEMPERATURE (°C)
–50 –25
1.19
FB VOLTAGE (V)
1.21
1.24
0
50
75
3580 G05
1.20
1.23
1.22
25
100
125
V
OUT
50mV/DIV
AC COUPLED
V
SW
10V/DIV
I
L
0.5A/DIV
200ns/DIV
3580 G06
TEMPERATURE (°C)
–50
FREQUENCY (MHz)
1.9
2.1
2.3
3580 G07
1.7
1.5
1.1
0
50
100
1.3
2.7
R
T
= 35.7k
2.5
R
T
= 75k
FB VOLTAGE (V)
0
0
NORMALIZED OSCILLATOR FREQUENCY (F/F
NOM
)
1/4
1/2
T
A
= –35°C
T
A
= 25°C
T
A
= 100°C
1/3
1
0.2 0.4
INVERTING
CONFIGURATIONS
BOOSTING
CONFIGURATIONS
0.6 0.8
3580 G08
1.0 1.2
TEMPERATURE (°C)
–50
2.20
V
IN
VOLTAGE (V)
2.22
2.26
2.28
2.30
2.40
2.34
0
50
3580 G09
2.24
2.36
2.38
2.32
100
LT3580
5
3580fg
TYPICAL PERFORMANCE CHARACTERISTICS
SHDN Pin Current SHDN Pin Current Active/Lockout Threshold
T
A
= 25°C unless otherwise specified
PIN FUNCTIONS
FB (Pin 1): Positive and Negative Feedback Pin. For a
boost or inverting converter, tie a resistor from the FB pin
to V
OUT
according to the following equations:
R
FB
=
V
OUT
−1.215
()
83.3 • 10
−6
; Boost or SEPIC Converter
R
FB
=
V
OUT
+ 5mV
()
83.3 • 10
−6
; Inverting Converter
VC (Pin 2): Error Amplifier Output Pin. Tie external
compensation network to this pin.
V
IN
(Pin 3): Input Supply Pin. Must be locally bypassed.
SW (Pin 4): Switch Pin. This is the collector of the internal
NPN Power switch. Minimize the metal trace area connec-
ted to this pin to minimize EMI.
SHDN (Pin 5): Shutdown Pin. In conjunction with the
UVLO (undervoltage lockout) circuit, this pin is used
to enable/disable the chip and restart the soft-start
sequence. Drive below 1.24V (LT3580E, LT3580I) or 1.22V
(LT3580H, LT3580MP) to disable the chip. Drive above
1.38V (LT3580E, LT3580I) or 1.40V (LT3580H, LT3580MP)
to activate chip and restart the soft-start sequence. Do
not float this pin.
RT (Pin 6): Timing Resistor Pin. Adjusts the switching
frequency. Place a resistor from this pin to ground to set
the frequency to a fixed free running level. Do not float
this pin.
SS (Pin 7): Soft-Start Pin. Place a soft-start capacitor here.
Upon start-up, the SS pin will be charged by a (nominally)
275k resistor to about 2.2V.
SYNC (Pin 8): To synchronize the switching frequency to
an outside clock, simply drive this pin with a clock. The
high voltage level of the clock needs to exceed 1.3V, and
the low level should be less 0.4V. Drive this pin to less than
0.4V to revert to the internal free running clock. See the
Applications Information section for more information.
GND (Exposed Pad Pin 9): Ground. Exposed pad must
be soldered directly to local ground plane.
SHDN VOLTAGE (V)
0
0
SHDN PIN CURRENT (μA)
5
10
15
20
25
30
0.5 1
–50°C
1.5 2
3580 G10
100°C
20°C
SHDN VOLTAGE (V)
0
SHDN PIN CURRENT (μA)
200
250
–50°C
20°C
100°C
300
15 25
3580 G11
150
100
510
20 30
50
0
TEMPERATURE (°C)
–50
1.20
SHDN VOLTAGE (V)
1.22
1.26
1.28
1.30
1.40
1.34
0
50
3580 G12
1.24
1.36
1.38
1.32
100
SHDN RISING
SHDN FALLING
LT3580
6
3580fg
BLOCK DIAGRAM
The LT3580 uses a constant-frequency, current mode con-
trol scheme to provide excellent line and load regulation.
Refer to the Block Diagram which shows the LT3580 in a
boost configuration. At the start of each oscillator cycle,
the SR latch (SR1) is set, which turns on the power switch,
Q1. The switch current flows through the internal current
sense resistor generating a voltage proportional to the
switch current. This voltage (amplified by A4) is added
to a stabilizing ramp and the resulting sum is fed into the
positive terminal of the PWM comparator A3. When this
voltage exceeds the level at the negative input of A3, the SR
latch is reset, turning off the power switch. The level at the
negative input of A3 (VC pin) is set by the error amplifier A1
(or A2) and is simply an amplified version of the difference
between the feedback voltage (FB pin) and the reference
voltage (1.215V or 5mV depending on the configuration).
In this manner, the error amplifier sets the correct peak
current level to keep the output in regulation.
The LT3580 has a novel FB pin architecture that can be
used for either boost or inverting configurations. When
configured as a boost converter, the FB pin is pulled up
to the internal bias voltage of 1.215V by the R
FB
resistor
connected from V
OUT
to FB. Comparator A2 becomes
inactive and comparator A1 performs the inverting
amplification from FB to VC. When the LT3580 is in an
inverting configuration, the FB pin is pulled down to 5mV
by the R
FB
resistor connected from V
OUT
to FB. Comparator
A1 becomes inactive and comparator A2 performs the
noninverting amplification from FB to VC.
–
+
–
+
–
+
–
+
+
–
∑
7
5
3
1.215V
REFERENCE
ADJUSTABLE
OSCILLATOR
FREQUENCY
FOLDBACK
RAMP
GENERATOR
COMPARATOR
DISCHARGE
DETECT
SS
VC
275k
Q2
SR2
R
S
14.6k
14.6k
Q
SR1
A3
A4
A1
A2
SYNC
÷N
RT
SHDN
FB
1.3V
VC
C1
SW
0.01Ω
GND
R
T
R
FB
DRIVER
L1
D1
I
LIMIT
V
IN
V
OU
T
C
SS
C
C
C
IN
R
C
V
IN
SOFT-
START
SYNC
BLOCK
UVLO
R
S
Q
6
2
1
3580 BD
8
4
Q1
9
OPERATION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

LT3580IDD#PBF

Mfr. #:
Buy LT3580IDD#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2A Boost/Inverting Switching Regulator
Lifecycle:
New from this manufacturer.
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