LT3580
7
3580fg
OPERATION
Figure 1. SEPIC Topology Allows for the Input to Span
the Output Voltage. Coupled or Uncoupled Inductors
Can Be Used. Follow Noted Phasing if Coupled
Figure 2. Dual Inductor Inverting Topology Results in
Low Output Ripple. Coupled or Uncoupled Inductors
Can Be Used. Follow Noted Phasing if Coupled
D1
SHUTDOWN
L2
C3
L1
R1
V
IN
> V
OUT
OR
V
IN
= V
OUT
OR
V
IN
< V
OUT
V
OUT
V
IN
SW
3580 F01
LT3580
RT
RC
C2
SHDN
GND
FB
VC
SYNC SS
RT
CC
C
SS
C1
+
+
D1
SHUTDOWN
C3
L1
R1
V
IN
V
OUT
V
IN
SW
3580 F02
LT3580
RT
RC
C2
SHDN
GND
FB
VC
SYNC SS
RT
CC
C
SS
C1
L2
+
+
••
SEPIC Topology
The LT3580 can be configured as a SEPIC (single-ended
primary inductance converter). This topology allows for
the input to be higher, equal, or lower then the desired
output voltage. Output disconnect is inherently built into
the SEPIC topology, meaning no DC path exists between the
input and output. This is useful for applications requiring
the output to be disconnected from the input source when
the circuit is in shutdown.
Inverting Topology
The LT3580 can also work in a dual inductor inverting
topology. The part’s unique feedback pin allows for the
inverting topology to be built by simply changing the
connection of external components. This solution results
in very low output voltage ripple due to inductor L2 in
series with the output. Abrupt changes in output capacitor
current are eliminated because the output inductor deliv-
ers current to the output during both the off-time and the
on-time of the LT3580 switch.
Start-Up Operation
Several functions are provided to enable a very clean
start-up for the LT3580.
• First, the SHDN pin voltage is monitored by an internal
voltage reference to give a precise turn-on voltage level.
An external resistor (or resistor divider) can be connected
from the input power supply to the SHDN pin to provide
a user-programmable undervoltage lockout function.
Second, the soft-start circuitry provides for a gradual
ramp-up of the switch current. When the part is brought
out of shutdown, the external SS capacitor is first
discharged (providing protection against SHDN pin
glitches and slow ramping), then an integrated 275k
resistor pulls the SS pin up to ~2.2V. By connecting an
external capacitor to the SS pin, the voltage ramp rate
on the pin can be set. Typical values for the soft-start
capacitor range from 100nF to 1μF.
Finally, the frequency foldback circuit reduces the
switching frequency when the FB pin is in a nominal range
of 350mV to 900mV. This feature reduces the minimum
duty cycle that the part can achieve thus allowing better
control of the switch current during start-up. When the
FB voltage is pulled outside of this range, the switching
frequency returns to normal.
Current Limit and Thermal Shutdown Operation
The LT3580 has a current limit circuit not shown in the
Block Diagram. The switch current is consistently moni-
tored and not allowed to exceed the maximum switch
current at a given duty cycle (see the Electrical Charac-
teristics table). If the switch current reaches this value,
the SR latch (SR1) is reset regardless of the state of the
comparator (A1/A2). Also not shown in the Block Diagram
is the thermal shutdown circuit. If the temperature of the
part exceeds approximately 165°C, the SR2 latch is set
regardless of the state of the comparator (A1/A2). A full
soft-start cycle will then be initiated. The current limit and
thermal shutdown circuits protect the power switch as well
as the external components connected to the LT3580.
LT3580
8
3580fg
Setting Output Voltage
The output voltage is set by connecting a resistor (R
FB
)
from V
OUT
to the FB pin. R
FB
is determined from the
following equation:
R
FB
=
|V
OUT
V
FB
|
83.3µA
where V
FB
is 1.215V (typical) for non-inverting topologies
(i.e., boost and SEPIC regulators) and 5mV (typical) for
inverting topologies (see the Electrical Characteristics).
Power Switch Duty Cycle
In order to maintain loop stability and deliver adequate
current to the load, the power NPN (Q1 in the Block Dia-
gram) cannot remain “on” for 100% of each clock cycle.
The maximum allowable duty cycle is given by:
DC
MAX
=
(T
P
Min Off Time)
T
P
100%
where T
P
is the clock period and Min Off Time (found in
the Electrical Characteristics) is typically 60ns.
The application should be designed so that the operating
duty cycle does not exceed DC
MAX
.
Duty cycle equations for several common topologies are
given below, where V
D
is the diode forward voltage drop
and V
CESAT
is typically 300mV at 1.5A.
For the boost topology:
DC
V
OUT
V
IN
+ V
D
V
OUT
+ V
D
V
CESAT
For the SEPIC or dual inductor inverting topology (see
Figures 1 and 2):
DC
V
D
+|V
OUT
|
V
IN
+ |V
OUT
| + V
D
V
CESAT
The LT3580 can be used in configurations where the duty
cycle is higher than DC
MAX
, but it must be operated in the
discontinuous conduction mode so that the effective duty
cycle is reduced.
APPLICATIONS INFORMATION
Inductor Selection
General Guidelines
: The high frequency operation of the
LT3580 allows for the use of small surface mount inductors.
For high efficiency, choose inductors with high frequency
core material, such as ferrite, to reduce core losses. To
improve efficiency, choose inductors with more volume
for a given inductance. The inductor should have low
DCR (copper wire resistance) to reduce I
2
R losses, and
must be able to handle the peak inductor current without
saturating. Note that in some applications, the current
handling requirements of the inductor can be lower, such
as in the SEPIC topology, where each inductor only carries
a fraction of the total switch current. Molded chokes or chip
inductors usually do not have enough core area to sup-
port peak inductor currents in the 2A to 3A range. To
minimize radiated noise, use a toroidal or shielded inductor.
Note that the inductance of shielded types will drop more
as current increases, and will saturate more easily. See
Table 1 for a list of inductor manufacturers. Thorough lab
evaluation is recommended to verify that the following
guidelines properly suit the final application.
Table 1.Inductor Manufacturers
Coilcraft DO3316P, MSS7341 and LPS4018
Series
www.coilcraft.com
Coiltronics DR, LD and CD Series www.coiltronics.com
Murata LQH55D and LQH66S Series www.murata.com
Sumida CDRH5D18B/HP, CDR6D23MN,
CDRH6D26/HP, CDRH6D28,
CDR7D28MN and CDRH105R Series
www.sumida.com
TDK RLF7030 and VLCF4020 Series www.tdk.com
Würth WE-PD and WE-PD2 Series www.we-online.com
Minimum Inductance
: Although there can be a tradeoff with
efficiency, it is often desirable to minimize board space by
choosing smaller inductors. When choosing an inductor,
there are two conditions that limit the minimum inductance;
(1) providing adequate load current, and (2) avoidance of
subharmonic oscillation. Choose an inductance that is high
enough to meet both of these requirements.
Adequate Load Current
: Small value inductors result in
increased ripple currents and thus, due to the limited peak
switch current, decrease the average current that can be
LT3580
9
3580fg
APPLICATIONS INFORMATION
provided to a load (I
OUT
). In order to provide adequate
load current, L should be at least:
L >
DC • V
IN
2(f) I
LIM
|V
OUT
|• I
OUT
V
IN
η
for boost, topologies, or:
L >
DC • V
IN
2(f) I
LIM
V
OUT
•I
OUT
V
IN
η
I
OUT
for the SEPIC and inverting topologies.
where:
L = L1||L2 for uncoupled dual inductor topologies
DC = switch duty cycle (see previous section)
I
LIM
= switch current limit, typically about 2.4A at 50%
duty cycle (see the Typical Performance Characteristics
section).
η = power conversion efficiency (typically 88% for
boost and 75% for dual inductor topologies at high
currents).
f = switching frequency
Negative values of L indicate that the output load current
I
OUT
exceeds the switch current limit capability of the
LT3580.
Avoiding Subharmonic Oscillations
: The LT3580’s internal
slope compensation circuit will prevent subharmonic oscil-
lations that can occur when the duty cycle is greater than
50%, provided that the inductance exceeds a minimum
value. In applications that operate with duty cycles greater
than 50%, the inductance must be at least:
L >
V
IN
•2DC1
()
(1DC) (f)
for boost, coupled inductor SEPIC, and coupled inductor
inverting topologies, or:
L1 L2>
V
IN
•2DC1
()
(1DC) (f)
for the uncoupled inductor SEPIC and uncoupled inductor
inverting topologies.
Maximum Inductance
: Excessive inductance can reduce
current ripple to levels that are difficult for the current com-
parator (A3 in the Block Diagram) to cleanly discriminate,
thus causing duty cycle jitter and/or poor regulation. The
maximum inductance can be calculated by:
L
MAX
=
V
IN
–V
CESAT
I
MINRIPPLE
DC
f
where L
MAX
is L1||L2 for uncoupled dual inductor topolo-
gies and I
MIN-RIPPLE
is typically 95mA.
Current Rating
: Finally, the inductor(s) must have a rating
greater than its peak operating current to prevent inductor
saturation resulting in efficiency loss. In steady state, the
peak input inductor current (continuous conduction mode
only) is given by:
I
L1PEAK
=
V
OUT
•I
OUT
V
IN
η
+
V
IN
•DC
2•L1f
for the boost, uncoupled inductor SEPIC and uncoupled
inductor inverting topologies.
For uncoupled dual inductor topologies, the peak output
inductor current is given by:
I
L2PEAK
=I
OUT
+
V
OUT
•1DC
()
2•L2•f
For the coupled inductor topologies:
I
OUT
1+
V
OUT
η•V
IN
+
V
IN
•DC
2•Lf
Note: Inductor current can be higher during load transients.
It can also be higher during start-up if inadequate soft-start
capacitance is used.
Capacitor Selection
Low ESR (equivalent series resistance) capacitors should
be used at the output to minimize the output ripple voltage.
Multilayer ceramic capacitors are an excellent choice, as
they have an extremely low ESR and are available in very
small packages. X5R or X7R dielectrics are preferred, as

LT3580IDD#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2A Boost/Inverting Switching Regulator
Lifecycle:
New from this manufacturer.
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