AD9200
–9–
REV. E
SUMMARY OF MODES
VOLTAGE REFERENCE
1 V Mode the internal reference may be set to 1 V by connect-
ing REFSENSE and VREF together.
2 V Mode the internal reference my be set to 2 V by connecting
REFSENSE to analog ground
External Divider Mode the internal reference may be set to a
point between 1 V and 2 V by adding external resistors. See
Figure 16f.
External Reference Mode enables the user to apply an exter-
nal reference to REFTS, REFBS and VREF pins. This mode
is attained by tying REFSENSE to VDD.
REFERENCE BUFFER
Center Span Mode midscale is set by shorting REFTS and
REFBS together and applying the midscale voltage to that point
The MODE pin is set to AVDD/2. The analog input will swing
about that midscale point.
Top/Bottom Mode sets the input range between two points.
The two points are between 1 V and 2 V apart. The Top/Bottom
Mode is enabled by tying the MODE pin to AVDD.
ANALOG INPUT
Differential Mode is attained by driving the AIN pin as one
differential input and shorting REFTS and REFBS together and
driving them as the second differential input. The MODE pin
is tied to AVDD/2. Preferred mode for optimal distortion
performance.
Single-Ended is attained by driving the AIN pin while the
REFTS and REFBS pins are held at dc points. The MODE pin is
tied to AVDD.
Single-Ended/Clamped (AC Coupled) the input may be
clamped to some dc level by ac coupling the input. This is done
by tying the CLAMPIN to some dc point and applying a pulse
to the CLAMP pin. MODE pin is tied to AVDD.
SPECIAL
AD876 Mode enables users of the AD876 to drop the AD9200
into their socket. This mode is attained by floating or grounding
the MODE pin.
INPUT AND REFERENCE OVERVIEW
Figure 16, a simplified model of the AD9200, highlights the
relationship between the analog input, AIN, and the reference
voltages, REFTS, REFBS and VREF. Like the voltages applied
to the resistor ladder in a flash A/D converter, REFTS and
REFBS define the maximum and minimum input voltages to
the A/D.
The input stage is normally configured for single-ended opera-
tion, but allows for differential operation by shorting REFTS
and REFBS together to be used as the second input.
SHA
AIN
REFTS
REFBS
A/D
CORE
AD9200
Figure 15. AD9200 Equivalent Functional Input Circuit
In single-ended operation, the input spans the range,
REFBS AIN REFTS
where REFBS can be connected to GND and REFTS con-
nected to VREF. If the user requires a different reference range,
REFBS and REFTS can be driven to any voltage within the
power supply rails, so long as the difference between the two is
between 1 V and 2 V.
In differential operation, REFTS and REFBS are shorted to-
gether, and the input span is set by VREF,
(REFTSVREF/2) AIN (REFTS + VREF/2)
where VREF is determined by the internal reference or brought
in externally by the user.
The best noise performance may be obtained by operating the
AD9200 with a 2 V input range. The best distortion perfor-
mance may be obtained by operating the AD9200 with a 1 V
input range.
REFERENCE OPERATION
The AD9200 can be configured in a variety of reference topolo-
gies. The simplest configuration is to use the AD9200’s onboard
bandgap reference, which provides a pin-strappable option to
generate either a 1 V or 2 V output. If the user desires a refer-
ence voltage other than those two, an external resistor divider
can be connected between VREF, REFSENSE and analog
ground to generate a potential anywhere between 1 V and 2 V.
Another alternative is to use an external reference for designs
requiring enhanced accuracy and/or drift performance. A
third alternative is to bring in top and bottom references,
bypassing VREF altogether.
Figures 16d, 16e and 16f illustrate the reference and input ar-
chitecture of the AD9200. In tailoring a desired arrangement,
the user can select an input configuration to match drive circuit.
Then, moving to the reference modes at the bottom of the
figure, select a reference circuit to accommodate the offset and
amplitude of a full-scale signal.
Table I outlines pin configurations to match user requirements.
AD9200
–10–
REV. E
SHA
A2
10kV
10kV
10kV
A/D
CORE
4.2kV
TOTAL
REFTS
REFBS
10mF
0.1mF
REFTF
REFBF
0.1mF
AIN
+F/S RANGE OBTAINED
FROM VREF PIN OR
EXTERNAL REF
–F/S RANGE OBTAINED
FROM VREF PIN OR
EXTERNAL REF
0.1mF
MODE
(AVDD)
+FS
–FS
AD9200
10kV
a. Top/Bottom Mode
V
MAXIMUM MAGNITUDE OF V
IS DETERMINED BY INTERNAL
REFERENCE AND TURNS RATIO
MODE
INTERNAL
REF
AVDD/2
SHA
10kV
10kV
10kV
A/D
CORE
4.2kV
TOTAL
10mF
0.1mF
REFTF
REFBF
0.1mF
AIN
0.1mF
AD9200
10kV
A2
REFTS
REFBS
AVDD/2
c. Differential Mode
A1
1V
AVSS
REFSENSE
VREF
(1V)
AD9200
0.1mF 1.0mF
d. 1 V Reference
0.01mF 1.0mF
A1
10kV
10kV
1V
AVSS
REFSENSE
VREF
(2V)
AD9200
e. 2 V Reference
A1
1V
AVSS
REFSENSE
VREF
(= 1 + R
A
/R
B
)
R
A
R
B
INTERNAL 10K REF RESISTORS ARE
SWITCHED OPEN BY THE PRESENSE
OF R
A
AND R
B
.
AD9200
0.1mF 1.0mF
f. Variable Reference
(Between 1 V and 2 V)
Figure 16.
A1
1V
REFSENSE
AVDD
VREF
AD9200
g. Internal Reference Disable
(Power Reduction)
MODE
INTERNAL
REF
MIDSCALE OFFSET
VOLTAGE IS DERIVED
FROM INTERNAL OR
EXTERNAL REF
MIDSCALE
V*
AVDD/2
* MAXIMUM MAGNITUDE OF V IS DETERMINED
BY INTERNAL REFERENCE
10kV
10kV
10kV
A/D
CORE
4.2kV
TOTAL
REFTS
REFBS
10mF
0.1mF
REFTF
REFBF
0.1mF
AIN
0.1mF
AD9200
10kV
A2
SHA
b. Center Span Mode
AD9200
–11–
REV. E
The actual reference voltages used by the internal circuitry of
the AD9200 appear on REFTF and REFBF. For proper opera-
tion, it is necessary to add a capacitor network to decouple these
pins. The REFTF and REFBF should be decoupled for all
internal and external configurations as shown in Figure 17.
AD9200
REFTF
REFBF
0.1mF
0.1mF
10mF
0.1mF
Figure 17. Reference Decoupling Network
Note: REFTF = reference top, force
REFBF = reference bottom, force
REFTS = reference top, sense
REFBS = reference bottom, sense
INTERNAL REFERENCE OPERATION
Figures 18, 19 and 20 show example hookups of the AD9200
internal reference in its most common configurations. (Figures
18 and 19 illustrate top/bottom mode while Figure 20 illustrates
center span mode). Figure 29 shows how to connect the AD9200
for 1 V p-p differential operation. Shorting the VREF pin
directly to the REFSENSE pin places the internal reference
amplifier, A1, in unity-gain mode and the resultant reference
output is 1 V. In Figure 18 REFBS is grounded to give an input
range from 0 V to 1 V. These modes can be chosen when the
supply is either +3 V or +5 V. The VREF pin must be bypassed to
AVSS (analog ground) with a 1.0 µF tantalum capacitor in
parallel with a low inductance, low ESR, 0.1 µF ceramic capacitor.
1V
0V
MODE
AVDD
10kV
10kV
10kV
A/D
CORE
4.2kV
TOTAL
REFTS
REFBS
10mF
0.1mF
REFTF
REFBF
0.1mF
AIN
0.1mF
AD9200
10kV
REF
SENSE
VREF
A1
1V
A2
SHA
0.1mF1.0mF
Figure 18. Internal Reference 1 V p-p Input Span
(Top/Bottom Mode)
Figure 19 shows the single-ended configuration for 2 V p-p
operation. REFSENSE is connected to GND, resulting in a 2 V
reference output.
2V
0V
MODE
AVDD
A2
10kV
10kV
10kV
A/D
CORE
4.2kV
TOTAL
REFTS
REFBS
10mF
0.1mF
REFTF
REFBF
0.1mF
AIN
0.1mF
AD9200
10kV
REF
SENSE
VREF
A1
1V
SHA
0.1mF
1.0mF
Figure 19. Internal Reference, 2 V p-p Input Span
(Top/Bottom Mode)
Figure 20 shows the single-ended configuration that gives the
good high frequency dynamic performance (SINAD, SFDR).
To optimize dynamic performance, center the common-mode
voltage of the analog input at approximately 1.5 V. Connect the
shorted REFTS and REFBS inputs to a low impedance 1.5 V
source. In this configuration, the MODE pin is driven to a volt-
age at midsupply (AVDD/2).
Maximum reference drive is 1 mA. An external buffer is re-
quired for heavier loads.
AVDD/2
+1.5V
2V
1V
MODE
10kV
10kV
10kV
A/D
CORE
4.2kV
TOTAL
REFTS
REFBS
10mF
0.1mF
REFTF
REFBF
0.1mF
AIN
0.1mF
AD9200
10kV
REF
SENSE
VREF
1V
SHA
A2
A1
0.1mF
1.0mF
Figure 20. Internal Reference 1 V p-p Input Span,
(Center Span Mode)

AD9200JRSZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 10B 20MSPS 80mW CMOS
Lifecycle:
New from this manufacturer.
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