AD9200
–15–
REV. E
DIFFERENTIAL INPUT OPERATION
The AD9200 will accept differential input signals. This function
may be used by shorting REFTS and REFBS and driving them
as one leg of the differential signal (the top leg is driven into
AIN). In the configuration below, the AD9200 is accepting a
1 V p-p signal. See Figure 29.
AIN
REFTS
REFTF
REFBF
REFBS
AD9200
0.1mF
10mF
0.1mF
0.1mF
2V
1V
AVDD/2
VREF
REFSENSE
MODE
AVDD/2
0.1mF
1.0mF
Figure 29. Differential Input
AD876 MODE OF OPERATION
The AD9200 may be dropped into the AD876 socket. This will
allow AD876 users to take advantage of the reduced power
consumption realized when running the AD9200 on a 3.0 V
analog supply.
Figure 30 shows the pin functions of the AD876 and AD9200.
The grounded REFSENSE pin and floating MODE pin effec-
tively put the AD9200 in the external reference mode. The
external reference input for the AD876 will now be placed on
the reference pins of the AD9200.
The clamp controls will be grounded by the AD876 socket. The
AD9200 has a 3 clock cycle delay compared to a 3.5 cycle delay
of the AD876.
4V
2V
0.1mF
0.1mF
AVDD
10mF
0.1mF
4V
2V
AIN
REFTS
REFTF
REFBF
REFBS
CLAMP
REFSENSE
AD9200
MODENC
CLAMPIN
OTR
VREF
0.1mF
Figure 30. AD876 Mode
CLOCK INPUT
The AD9200 clock input is buffered internally with an inverter
powered from the AVDD pin. This feature allows the AD9200
to accommodate either +5 V or +3.3 V CMOS logic input sig-
nal swings with the input threshold for the CLK pin nominally
at AVDD/2.
The pipelined architecture of the AD9200 operates on both
rising and falling edges of the input clock. To minimize duty
cycle variations the recommended logic family to drive the clock
input is high speed or advanced CMOS (HC/HCT, AC/ACT)
logic. CMOS logic provides both symmetrical voltage threshold
levels and sufficient rise and fall times to support 20 MSPS
operation. The AD9200 is designed to support a conversion rate
of 20 MSPS; running the part at slightly faster clock rates may
be possible, although at reduced performance levels. Conversely,
some slight performance improvements might be realized by
clocking the AD9200 at slower clock rates.
t
CL
t
CH
t
C
25ns
DATA 1
DATA
OUTPUT
INPUT
CLOCK
ANALOG
INPUT
S1
S2
S3
S4
Figure 31. Timing Diagram
The power dissipated by the output buffers is largely propor-
tional to the clock frequency; running at reduced clock rates
provides a reduction in power consumption.
DIGITAL INPUTS AND OUTPUTS
Each of the AD9200 digital control inputs, THREE-STATE
and STBY are reference to analog ground. The clock is also
referenced to analog ground.
The format of the digital output is straight binary (see Figure
32). A low power mode feature is provided such that for STBY
= HIGH and the clock disabled, the static power of the AD9200
will drop below 5 mW.
OTR
–FS
–FS+1LSB
+FS–1LSB
+FS
Figure 32. Output Data Format
HIGH
IMPEDANCE
t
DHZ
t
DEN
THREE-
STATE
DATA
(D0–D9)
Figure 33. Three-State Timing Diagram
AD9200
–16–
REV. E
APPLICATIONS
DIRECT IF DOWN CONVERSION USING THE AD9200
Sampling IF signals above an ADC’s baseband region (i.e., dc
to F
S
/2) is becoming increasingly popular in communication
applications. This process is often referred to as Direct IF Down
Conversion or Undersampling. There are several potential ben-
efits in using the ADC to alias (i.e., or mix) down a narrowband
or wideband IF signal. First and foremost is the elimination of a
complete mixer stage with its associated amplifiers and filters,
reducing cost and power dissipation. Second is the ability to
apply various DSP techniques to perform such functions as
filtering, channel selection, quadrature demodulation, data
reduction, detection, etc. A detailed discussion on using this
technique in digital receivers can be found in Analog Devices
Application Notes AN-301 and AN-302.
In Direct IF Down Conversion applications, one exploits the
inherent sampling process of an ADC in which an IF signal
lying outside the baseband region can be aliased back into the
baseband region in a similar manner that a mixer will down-
convert an IF signal. Similar to the mixer topology, an image
rejection filter is required to limit other potential interfering
signals from also aliasing back into the ADC’s baseband region.
A tradeoff exists between the complexity of this image rejection
filter and the sample rate as well as dynamic range of the ADC.
The AD9200 is well suited for various narrowband IF sampling
applications. The AD9200’s low distortion input SHA has a
full-power bandwidth extending to 300 MHz thus encompassing
many popular IF frequencies. A DNL of ±0.5 LSB (typ) com-
bined with low thermal input referred noise allows the AD9200 in
the 2 V span to provide 60 dB of SNR for a baseband input sine
wave. Also, its low aperture jitter of 2 ps rms ensures minimum
SNR degradation at higher IF frequencies. In fact, the AD9200
is capable of still maintaining 56 dB of SNR at an IF of 135 MHz
with a 1 V (i.e., 4 dBm) input span. Note, although the AD9200
will typically yield a 3 to 4 dB improvement in SNR when con-
figured for the 2 V span, the 1 V span provides the optimum
full-scale distortion performance. Furthermore, the 1 V span
reduces the performance requirements of the input driver cir-
cuitry and thus may be more practical for system implementa-
tion purposes.
Figure 34 shows a simplified schematic of the AD9200 config-
ured in an IF sampling application. To reduce the complexity of
the digital demodulator in many quadrature demodulation ap-
plications, the IF frequency and/or sample rate are selected such
that the bandlimited IF signal aliases back into the center of the
ADC’s baseband region (i.e., F
S
/4). For example, if an IF sig-
nal centered at 45 MHz is sampled at 20 MSPS, an image of
this IF signal will be aliased back to 5.0 MHz which corre-
sponds to one quarter of the sample rate (i.e., F
S
/4). This
demodulation technique typically reduces the complexity of the
post digital demodulator ASIC which follows the ADC.
To maximize its distortion performance, the AD9200 is config-
ured in the differential mode with a 1 V span using a transformer.
The center tap of the transformer is biased at midsupply via a
resistor divider. Preceding the AD9200 is a bandpass filter as
well as a 32 dB gain stage. A large gain stage may be required
to compensate for the high insertion losses of a SAW filter used
for image rejection. The gain stage will also provide adequate
isolation for the SAW filter from the charge “kick back” currents
associated with AD9200’s input stage.
The gain stage can be realized using one or two cascaded
AD8009 op amps amplifiers. The AD8009 is a low cost, 1 GHz,
current-feedback op amp having a 3rd order intercept character-
ized up to 250 MHz. A passive bandpass filter following the
AD8009 attenuates its dominant 2nd order distortion products
which would otherwise be aliased back into the AD9200’s
baseband region. Also, it reduces any out-of-band noise which
would also be aliased back due to the AD9200’s noise band-
width of 220+ MHz. Note, the bandpass filters specifications
are application dependent and will affect both the total distor-
tion and noise performance of this circuit.
The distortion and noise performance of an ADC at the given
IF frequency is of particular concern when evaluating an ADC
for a narrowband IF sampling application. Both single-tone and
dual-tone SFDR vs. amplitude are very useful in an assessing an
ADC’s noise performance and noise contribution due to aper-
ture jitter. In any application, one is advised to test several units
of the same device under the same conditions to evaluate the
given applications sensitivity to that particular device.
0.1mF
AIN
REFTS
AD9200
REFBS
REFSENSE
VREF
AVDD
200V
1kV
1kV
50V
93.1V
280V
50V
22.1V
200V
SAW
FILTER
OUTPUT
50V
BANDPASS
FILTER
G
1
= 20dB G
2
= 12dB L-C
MINI CIRCUITS
T4 - 6T
1:4
0.1mF1.0mF
Figure 34. Simplified AD9200 IF Sampling Circuit
AD9200
–17–
REV. E
Figures 35–38 combine the dual-tone SFDR as well as single
tone SFDR and SNR performance at IF frequencies of 45 MHz,
70 MHz, 85 MHz and 135 MHz. Note, the SFDR vs. ampli-
tude data is referenced to dBFS while the single tone SNR data
is referenced to dBc. The performance characteristics in these
figures are representative of the AD9200 without the AD8009.
The AD9200 was operated in the differential mode (via trans-
former) with a 1 V span at 20 MSPS. The analog supply
(AVDD) and the digital supply (DRVDD) were set to +5 V and
3.3 V, respectively.
90
80
0
–60 0–40 –20
70
60
30
20
INPUT POWER LEVEL – dBFS
50
40
10
–10–50 –30
WORST CASE SPURIOUS – dBFS
SNR – dBc
SINGLE TONE SFDR
DUAL TONE SFDR
SNR
CLK = 20MSPS
SINGLE TONE – 45.52MHz
DUAL TONE– F
1
= 44.49MHz
– F
2
= 45.52MHz
Figure 35. SNR/SFDR for IF @ 45 MHz
90
80
0
–60 0–40 –20
70
60
30
20
INPUT POWER LEVEL – dBFS
50
40
10
–10–50 –30
WORST CASE SPURIOUS – dBFS
SNR – dBc
SINGLE TONE SFDR
DUAL TONE SFDR
SNR
CLK = 21.538MSPS
SINGLE TONE – 70.55MHz
DUAL TONE– F
1
= 69.50MHz
– F
2
= 70.55MHz
Figure 36. SNR/SFDR for IF @ 70 MHz
Although not presented, data was also taken with the insertion
of an AD8009 gain stage of 32 dB in the signal path. No
degradation in two-tone SFDR vs. amplitude was noted at an
IF of 45 MHz, 70 MHz and 85 MHz. However, at 135 MHz,
the AD8009 became the limiting factor in the distortion perfor-
mance until the two input tones were decreased to –15 dBFS
from their full-scale level of –6.5 dBFS. Note: the SNR perfor-
mance in each case degraded by approximately 0.5 dB due to
the AD8009’s in-band noise contribution.
90
80
0
–60 0–40 –20
70
60
30
20
INPUT POWER LEVEL – dBFS
50
40
10
–10–50 –30
WORST CASE SPURIOUS – dBFS
SNR – dBc
SINGLE TONE SFDR
DUAL TONE SFDR
SNR
CLK = 20MSPS
SINGLE TONE – 85.52MHz
DUAL TONE– F
1
= 84.49MHz
– F
2
= 85.52MHz
Figure 37. SNR/SFDR for IF @ 85 MHz
WORST CASE SPURIOUS – dBFS
SNR – dBc
90
80
0
–60 0–40 –20
70
60
30
20
INPUT POWER LEVEL – dBFS
50
40
10
–10–50 –30
SINGLE TONE SFDR
DUAL TONE SFDR
SNR
CLK = 20MSPS
SINGLE TONE – 135.52MHz
DUAL TONE – F
1
= 134.44MHz
– F
2
= 135.52MHz
Figure 38. SNR/SFDR for IF @ 135 MHz

AD9200JRSZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 10B 20MSPS 80mW CMOS
Lifecycle:
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