OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ISL8118IRZ-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
10
FN6325.3
August 12, 2014
Submit Document Feedback
voltage monitoring. A 10µA current source to GND is active
while the part is disabled, and is inactive when the part is
enabled. This provides functionality for programmable
hysteresis when the EN pin is used for voltage monitoring.
VFF (Pin 13)
The voltage at this pin is used for input voltage feed forward
compensation and sets the internal oscillator ramp peak to
peak amplitude at 0.16*VFF. An external RC filter may be
required at this pin in noisy input environments. The
minimum recommended VFF voltage is 2.97V.
VIN (Pin 14, Internal Linear Regulator Input)
This pin should be tied directly to the input rail when using
the internal or external linear regulator options. It provides
power to the External/Internal Linear drive circuitry. When
used with an external 3.3V to 5V supply, this pin should be
tied directly to PVCC.
EXDRV (Pin 15, External Linear Regulator Drive)
This pin allows the use of an external pass element to power
the IC for input voltages above 5.0V. It should be connected to
GND when using an external 5V supply or the internal linear
regulator. When using the external linear regulator option, this
pin should be connected to the gate of a PMOS pass element,
a pull-up resistor must be connected between the PMOS
device’s gate and source for proper operation.
PVCC (Pin 16, Driver Bias Voltage)
This pin is the output of the internal series linear regulator. It
also provides the bias for both bottom side and top side
MOSFET drivers. The maximum voltage differential between
PVCC and PGND is 6V. Its recommended operational
voltage range is 2.9V to 5.6V. At minimum, a 10µF capacitor
is required for decoupling PVCC to PGND. For proper
operation the PVCC capacitor must be within 150 mils of the
PVCC and the PGND pins and must be connected to these
pins with dedicated traces.
BGATE (Pin 17)
This pin provides the drive for the bottom side MOSFET and
should be connected to its gate.
PGND (Pin 18, Power Ground)
This pin connects to the bottom side MOSFET's source and
provides the ground return path for the lower MOSFET driver
and internal power circuitries. In addition, PGND is the return
path for the bottom side MOSFET’s rDS(ON) current sensing
circuit.
LX (Pin 19)
This pin connects to the source of the top side MOSFET and
the drain of the bottom side MOSFET. This pin represents
the return path for the top side gate driver. During normal
switching, this pin is used for top side and bottom side
current sensing.
TGATE (Pin 20)
This pin provides the drive for the top side MOSFET and
should be connected to its gate.
BOOT (Pin 21)
This pin provides the bootstrap bias for the top side driver.
The absolute maximum voltage differential between BOOT
and LX is 6.0V (including the voltage added due to the
overcharging of the bootstrap capacitor); its operational
voltage range is 2.5V to 5.6V with respect to LX. It is
recommended that a 2.2 resistor be placed in series with
the bootstrap diode to prevent over charging of the BOOT
capacitor during normal operation.
TSOC (Pin 22)
The top side sourcing current limit is set by connecting this
pin with a resistor and capacitor to the drain of the top side
MOSEFT. A 100µA current source develops a voltage
across the resistor which is then compared with the voltage
developed across the top side MOSFET. An initial ~120ns
blanking period is used to eliminate sampling error due to
the switching noise before the current is measured.
BSOC (Pin 23)
The bottom side source and sinking current limit is set by
placing a resistor (RBSOC) and capacitor between this pin
and PGND. A 100µA current source develops a voltage
across RBSOC which is then compared with the voltage
developed across the bottom side MOSFET when on. The
sinking current limit is set at 1x of the nominal sourcing limit
in ISL8118. An initial ~120ns blanking period is used to
eliminate the sampling error due to switching noise before
the current is measured.
FSET (Pin 24)
This pin provides oscillator switching frequency adjustment
by placing a resistor (RFSET) from this pin to GND.
COMP (Pin 25)
This pin is the error amplifier output. It should be connected
to the FB pin through the desired compensation network.
FB (Pin 26)
This pin is the inverting input of the error amplifier and has a
maximum usable voltage of VCC-1.8V. When using the
internal differential remote sense functionality, this pin
should be connected to VDIFF by a standard feedback
network. In the event the remote sense buffer is disabled,
the VDIFF pin should be connected to VOUT by a resistor
divider along with FB’s compensation network.
GND (Pin 27, Analog Ground)
Signal ground for the IC. All voltage levels are measured
with respect to this pin. This pin should not be left floating.
VDIFF (Pin 28)
This pin is the output of the differential remote sense
instrumentation amplifier. It is connected internally to the
ISL8118
11
FN6325.3
August 12, 2014
Submit Document Feedback
OV/UV/PGOOD comparators. The VDIFF pin should be
connected to the FB pin by a standard feedback network. In
the event that the remote sense buffer is disabled, the VDIFF
pin should be connected to VOUT by a resistor divider along
with FB’s compensation network. An RC filter should be used
if VDIFF is to be connected directly to FB instead of to VOUT
through a separate resistor divider network.
GND (Bottom Side Pad, Analog Ground)
Signal ground for the IC. All voltage levels are measured
with respect to this pin. This pin should not be left floating.
Functional Description
Initialization
The ISL8118 automatically initializes upon receipt of power
without requiring any special sequencing of the input
supplies. The Power-On Reset (POR) function continually
monitors the input supply voltages (PVCC,VFF, VCC) and
the voltage at the EN pin. Assuming the EN pin is pulled to
above ~0.50V, the POR function initiates soft-start operation
after all input supplies exceed their POR thresholds.
With all input supplies above their POR thresholds, driving
the EN pin above 0.50V initiates a soft-start cycle. In addition
to normal TTL logic, the enable pin can be used as a voltage
monitor with programmable hysteresis through the use of the
internal 10mA sink current and an external resistor divider.
This feature is especially designed for applications that have
input rails greater than a 3.3V and require specific input rail
POR and Hysteresis levels for better undervoltage
protection. Consider for a 12V application choosing
RUP = 100k and RDOWN = 5.76k there by setting the
rising threshold (VEN_RTH) to 10V and the falling threshold
(VEN_FTH) to 9V, for 1V of hysteresis (VEN_HYS). Care
should be taken to prevent the voltage at the EN pin from
exceeding VCC when using the programmable UVLO
functionality.
Soft-start
The POR function activates the internal 38µA OTA which
begins charging the external capacitor (C
SS
) on the SS pin to a
target voltage of VCC. The ISL8118’s soft-start logic continues
to charge the SS pin until the voltage on COMP exceeds the
bottom of the oscillator ramp, at which point, the driver outputs
are enabled, with the bottom side MOSFET first being held low
for 200ns to provide for charging of the bootstrap capacitor.
Once the driver outputs are enabled, the OTA’s target voltage is
then changed to the margined (if margining is being used)
reference voltage (V
REF_MARG
), and the SS pin is ramped up
or down accordingly. This method reduces start-up surge
currents due to a pre-charged output by inhibiting regulator
switching until the control loop enters its linear region. By
ramping the positive input of the error amplifier to VCC and
then to V
REF_MARG
, it is even possible to mitigate surge
currents from outputs that are pre-charged above the set output
voltage. As the SS pin connects directly to the non-inverting
input of the Error Amplifier, noise on this pin should be kept to a
minimum through careful routing and part placement. To
prevent noise injection into the error amplifier, the SS capacitor
should be located within 150 mils of the SS and GND pins.
Soft-start is declared done when the drivers have been enabled
and the SS pin is within ±3mV of V
REF_MARG
.
Power Good
The power good comparator references the voltage on the
soft-start pin to prevent accidental tripping during margining.
The trip points are shown on Figure 3. Additionally, power
good will not be asserted until after the completion of the
soft-start cycle. A 0.1µF capacitor at the PGDLY pin will add
an additional ~7.1ms delay to the assertion of power good.
PGDLY does not delay the deassertion of power good.
ISL8118
12
FN6325.3
August 12, 2014
Submit Document Feedback
Undervoltage and Overvoltage Protection
The Undervoltage (UV) and Overvoltage (OV) protection
circuitry compares the voltage on the VDIFF pin with the
reference that tracks with the margining circuitry to prevent
accidental tripping. UV and OV functionality is not enabled
until the end of soft-start.
An OV event is detected asynchronously and causes the top
side MOSFET to turn off, the bottom side MOSFET to turn
on (effectively a 0% duty cycle), and PGOOD to pull low. The
regulator stays in this state and overrides sourcing and
sinking OCP protections until the OV event is cleared.
A UV event is detected asynchronously and results in the
PGOOD pulling low.
Overcurrent Protection
The ISL8118 monitors both the top side MOSFET and bottom
side MOSFET for overcurrent events. Dual sensing allows the
ISL8118 to detect overcurrent faults at the very low and very
high duty cycles that can result from the ISL8118’s wide input
range. The OCP function is enabled with the drivers at start-up
and detects the peak current during each sensing period. A
resistor and a capacitor between the BSOC pin and GND set
the bottom side source and sinking current limits. A 100µA
current source develops a voltage across the resistor which is
then compared with the voltage developed across the bottom
side MOSFET at conduction mode. The measurement
comparator uses offset correcting circuitry to provide precise
current measurements with roughly ±2mV of offset error. An
~120ns blanking period, implemented on the upper and lower
MOSFET current sensing circuitries, is used to reduce the
current sampling error due to the leading-edge switching noise.
An additional 120ns low pass filter is used to further reduce
measurement error due to noise. In sourcing current
applications, the BSOC voltage is inverted and compared with
the voltage across the MOSFET while on. When this voltage
exceeds the BSOC set voltage, a sourcing OCP fault is
triggered. A 1000pF or greater filter capacitor should be used in
parallel with R
BSOC
to prevent on chip parasitics from
impacting the accuracy of the OCP measurement.
The ISL8118’s sinking current limit is set to the same voltage
as its sourcing limit. In sinking applications, when the voltage
across the MOSFET is greater than the voltage developed
across the resistor (RBSOC) a sinking OCP event is
triggered. To avoid non-synchronous operation at light load,
the peak-to-peak output inductor ripple current should not be
greater than twice of the sinking current limit.
The top side sourcing current limit is set by connecting the
TSOC pin with a resistor (R
TSOC
) and a capacitor to the drain
of the top side MOSEFT. A 100µA current source develops a
voltage across the resistor which is then compared with the
voltage developed across the top side MOSFET while on.
When the voltage drop across the MOSFET exceeds the
voltage drop across the resistor, a sourcing OCP event
occurs. A 1000pF or greater filter capacitor should be used in
parallel with R
TSOC
to prevent on chip parasitics from
impacting the accuracy of the OCP measurement and to
smooth the voltage across R
TSOC
in the presence of
switching noise on the input bus.
Sourcing OCP faults cause the regulator to disable (TGATE
and BGATE drives pulled low, PGOOD pulled low, soft-start
capacitor discharged) itself for a fixed period of time after which
a normal soft-start sequence is initiated. The period of time the
regulator waits before attempting a soft-start sequence is set by
three charge and discharge cycles of the soft-start capacitor.
ISL8118
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

ISL8118IRZ-T

Mfr. #:
Buy ISL8118IRZ-T
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers 3 3V-20V INPUT SYNC PWM CONT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet