ISL8118IRZ-T Datasheet ISL8118CRZ, ISL8118IRZ-T, ISL8118IRZ | P13-P15

FN6325.3

August 12, 2014

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Sinking OCP faults cause the bottom side MOSFET drive to

be disabled, effectively operating the ISL8118 in a

non-synchronous manner. The fault is maintained for three

clock cycles at which point it is cleared and normal operation

is restored. OVP fault implementation overrides sourcing

and sinking OCP events, immediately turning on the bottom

side MOSFET and turning off the top side MOSFET. The OC

trip point varies mainly due to the MOSFETs rDS(ON)

variations and system noise. To avoid overcurrent tripping in

the normal operating load range, find the RTSOC and/or

RBSOC resistor from the previous detailed equations with:

1. Maximum rDS(ON) at the highest junction temperature;

2. Minimum IBSOC and/or ITSOC from specification table;

3. Determine the overcurrent trip point greater than the

maximum output continuous current at maximum

inductor ripple current.

Frequency Programming

By tying a resistor to GND from FSET pin, the switching

frequency can be set between 250kHz and 2MHz.

Oscillator/VFF

The Oscillator is a triangle waveform, providing for leading

and falling edge modulation. The bottom of the oscillator

waveform is set at 1.0V. The ramp's peak-to-peak amplitude

is determined from the voltage on the VFF (Voltage Feed

Forward) pin by Equation 1:

An internal RC filter of 233k and 2pF (341kHz) provides

filtering of the VFF voltage. An external RC filter may be

required to augment this filter in the event that it is insufficient to

prevent noise injection or control loop interactions. Voltages

below 2.9V on the VFF pin may result in undesirable operation

due to extremely small peak-to-peak oscillator waveforms. The

oscillator waveform should not exceed VCC -1.0V. For high

VFF voltages the internal/external 5.6V linear regulator should

be used. 5.6V on VCC provides sufficient headroom for 100%

duty cycle operation when using the maximum VFF voltage of

22V. In the event of sustained 100% duty cycle operation,

defined as 32 clock cycles where no BG pulse is detected, BG

will be pulsed on to refresh the design’s Bootstrap capacitor.

Internal Series Linear Regulator

The VIN pin is connected to PVCC with a 2 internal series

linear regulator, which is internally compensated. The external

Series Linear regulator option should be used for applications

requiring pass elements of less than 2. When using the

internal regulator, the EXDRV pin should be connected directly

to GND. The PVCC and VIN pins should have a bypass

capacitor (at least 10µF on PVCC is required) connected to

PGND. For proper operation, the PVCC capacitor must be

within 150 mils of the PVCC and the PGND pins, and be

connected to these pins with dedicated traces. The internal

series linear regulator’s input (VIN) can range between 3.3V to

20V ±10%. The internal linear regulator is to provide power for

both the internal MOSFET drivers through the PVCC pin and

the analog circuitry through the VCC pin. The VCC pin should

be connected to the PVCC pin with an RC filter to prevent high

frequency driver switching noise from entering the analog

circuitry. When VIN drops below 5.6V, the pass element will

saturate; PVCC will track VIN, minus the dropout of the linear

regulator: PVCC = VIN-2xIVIN. When used with an external 5V

supply, the VIN pin should be tied directly to PVCC.

External Series Linear Regulator

The EXDRV pin provides sinking drive capability for an

external pass element linear regulator controller. The

external linear options are especially useful when the

internal linear dropout is too large for a given application.

When using the external linear regulator option, the EXDRV

pin should be connected to the gate of a PMOS device, and

a resistor should be connected between its gate and source.

A resistor and a capacitor should be connected from gate to

source to compensate the control loop. A PNP device can be

used instead of a PMOS device, in which case the EXDRV

pin should be connected to the base of the PNP pass

element. The maximum sinking capability of the EXDRV pin

is 0.5mA, and should not be exceeded if using an external

resistor for a PMOS device. The designer should take care

in designing a stable system when using external pass

elements. The VCC pin should be connected to the PVCC

pin with an RC filter to prevent high frequency driver

switching noise from entering the analog circuitry.

High Speed MOSFET Gate Driver

The integrated driver has similar drive capability and features

to Intersil's ISL6605 stand alone gate driver. The PWM

tri-state feature helps prevent a negative transient on the

output voltage when the output is being shut down. This

eliminates the Schottky diode that is used in some systems for

protecting the microprocessor from reversed-output-voltage

damage. See the ISL6605 datasheet for specification

parameters that are not defined in the current ISL8118

Electrical Specifications table.

VOSC

0.16 VFF=

(EQ. 1)

FIGURE 4. R

RESISTANCE vs FREQUENCY

100

100k 1M 10M

FREQUENCY (Hz)

RESISTANCE (k

Fs Hz1.178

10 R



0.973–

TO GND)

(EQ. 2)

ISL8118

FN6325.3

August 12, 2014

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A 1 to 2 resistor is recommended to be in series with the

bootstrap diode when using VCCs above 5.0V to prevent the

bootstrap capacitor from overcharging due to the negative

swing of the trailing edge of the LX node.

Margining Control

When MARGIN is pulled high or low, the positive or negative

margining functionality is respectively enabled. When

MARGIN is left floating, the function is disabled. Upon

positive margining, an internal buffer drives the OFSN pin

from VCC to maintain OFSP at 0.591V. The resistor divider,

RMARG and ROFSP, causes the voltage at OFSN to be

increased. Similarly, upon Negative margining, an internal

buffer drives the OFSP pin from VCC to maintain OFSN at

0.591V. The resistor divider, RMARG and ROFSN, causes

the voltage at OFSP to be increased. In both modes, the

voltage difference between OFSP and OFSN is then sensed

with an instrumentation amplifier and is converted to the

desired margining voltage by a 5:1 ratio. The maximum

designed margining range of the ISL8118 is ±200mV; this

sets the MINIMUM value of ROFSP or ROFSN at

approximately 5.9k for an RMARG of 10k for a MAXIMUM of

1V across RMARG.

The OFS pins are completely independent and can be set to

different margining levels. The maximum usable reference

voltage for the ISL8118 is VCC - 1.8V, and should not be

exceeded when using the margining functionality, i.e,

VREF_MARG < VCC - 1.8V.

An alternative calculation provides for a desired percentage

change in the output voltage when using the internal 0.591V

reference:

When not used in a design OFSP, OFSN, and MARGIN

should be left floating. To prevent damage to the part, OFSP

and OFSN should not be tied to VCC or PVCC.

Reference Output Buffer

The internal buffer’s output tracks the unmargined system

reference. It has a 19mA drive capability, with maximum and

minimum output voltage capabilities of VCC and GND

respectively. Its capacitive loading can range from 1µF to

above 17.6µF, which is designed for 1 to 8 DIMM systems in

DDR (Dual Data Rate) applications. 1µF of capacitance

should always be present on REFOUT. It is not designed to

drive a resistive load and any such load added to the system

should be kept above 300ktotal impedance.

Reference Input

The REFIN pin allows the user to bypass the internal 0.591V

reference with an external reference. Asynchronously, if

REFIN is NOT within ~800mV of VCC, the external reference

pin is used as the control reference instead of the internal

0.591V reference. The minimum usable REFIN voltage is

~60mV while the maximum is VCC - 1.8V - V

MARG

(if

present). The limitation is set by the error amplifier's maximum

common mode input range of VCC - 1.8V for the industrial

temperature ranges.

Internal Reference and System Accuracy

The internal reference is trimmed to 0.591V. The total DC

system accuracy of the system is within 0.85% over

commercial temperature range, and 1.25% over industrial

temperature range. System accuracy includes error amplifier

offset, OTA error, and bandgap error. Differential remote

sense offset error is not included. As a result, if the

differential remote sense is used, then an extra 3mV of offset

error enters the system. The use of REFIN may add up to

1.8mV of additional offset error.

Differential Remote Sense Buffer

The differential remote sense buffer is essentially an

instrumentation amplifier with unity gain. The offset is

trimmed to 3mV for high system accuracy. As with any

instrumentation amplifier, typically 6µA are sourced from the

VSENSN pin. The output of the remote sense buffer is

connected directly to the internal OV/UV comparator. As a

result, a resistor divider should be placed on the input of the

buffer for proper regulation, as shown in Figure 6. The

VDIFF pin should be connected to the FB pin by a standard

feed-back network. A small capacitor, C

SEN

in Figure 6, can

be added to filter out noise, typically C

SEN

is chosen so the

corresponding time constant does not reduce the overall

phase margin of the design, typically this is 2x to 10x

switching frequency of the regulator.

As some applications will not use the differential remote

sense, the output of the remote sense buffer can be disabled

(high impedance) by pulling VSENSN within 800mV of VCC.

MARG_POS

REF

---------------

MARG

OFSP

---------------------

=

(EQ. 3)

MARG_NEG

REF

---------------

MARG

OFSN

---------------------

=

(EQ. 4)

PCT_POS

MARG

OFSP

---------------------

=

(EQ. 5)

PCT_NEG

MARG

OFSN

---------------------

=

(EQ. 6)

FIGURE 5. SIMPLIFIED REFERENCE BUFFER

OTA

800mV

REF_MARG

ISL8118

STATE

MACHINE

REFERENCE

REF

= 0.591V

REFIN

REFOUT

VCC

MARGINING

BLOCK

ISL8118

FN6325.3

August 12, 2014

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As the VDIFF pin is connected internally to the

OV/UV/PGOOD comparator, an external resistor divider

must then be connected to VDIFF to provide correct voltage

information for the OV/UV comparator. An RC filter should

be used if VDIFF is to be connected directly to FB instead of

to VOUT through a separate resistor divider network. This

filter prevents noise injection from disturbing the

OV/UV/PGOOD comparators on VDIFF. VDIFF may also be

connected to the SS pin, which completely bypasses the

OV/UV/PGOOD functionality.

Application Guidelines

Layout Considerations

As in any high frequency switching converter, layout is very

important. Switching current from one power device to

another can generate voltage transients across the

impedances of the interconnecting bond wires and circuit

traces. These interconnecting impedances should be

minimized by using wide, short printed circuit traces. The

critical components should be located as close together as

possible using ground plane construction or single point

grounding.

Figure 7 shows the critical power components of the

converter. To minimize the voltage overshoot/undershoot the

interconnecting wires indicated by heavy lines should be part

of ground or power plane in a printed circuit board. The

components shown in Figure 8 should be located as close

together as possible. Please note that the capacitors CIN

and CO each represent numerous physical capacitors.

Locate the ISL8118 within 3 inches of the MOSFETs, Q1 and

Q2. The circuit traces for the MOSFETs’ gate and source

connections from the ISL8118 must be sized to handle up to

4A peak current.

Proper grounding of the IC is important for correct operation in

noisy environments. The PGND pin should be connected to

board ground at the source of the bottom side MOSFET with a

wide short trace. The GND pin should be connected to a large

copper fill under the IC which is subsequently connected to

board ground at a quite location on the board, typically found

at an input or output bulk (electrolytic) capacitor.

VSENSN

VSENSP

COMP

VDIFF

OV/UV

ERROR AMP

COMP

SEN

800mV

VCC

10

VOUT (LOCAL)

GND (LOCAL)

VSENSE+

GAIN = 1

VSENSE-

FIGURE 6. SIMPLIFIED UNITY GAIN DIFFERENITAL SENSING IMPLEMENTATION

(REMOTE)

PGND

BGATE

TGATE

FIGURE 7. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

OUT

RETURN

ISL8118

LOAD

FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

+5V

ISL8118

PGND

PVCC

BOOT

OUT

LOAD

BOOT

PVCC

GND

ISL8118

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

ISL8118IRZ-T

Mfr. #:

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Manufacturer:

Renesas / Intersil

Description:

Switching Controllers 3 3V-20V INPUT SYNC PWM CONT

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ISL8118IRZ-T

ISL8118IRZ-T

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