19
FN6325.3
August 12, 2014
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
For additional products, see www.intersil.com/en/products.html
Submit Document Feedback
for the input capacitor of a buck regulator is approximated in
the following.
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-
GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
MOSFET Selection/Considerations
The ISL8118 requires 2 N-Channel power MOSFETs. These
should be selected based upon rDS(ON), gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the top and the bottom MOSFETs. These
losses are distributed between the two MOSFETs according
to duty factor (see the following equations). The upper
MOSFET exhibits turn-on and turn-off switching losses as
well as the reverse recover loss, while the synchronous
rectifier exhibits body-diode conduction losses during the
leading and trailing edge dead times.
where D is the duty cycle = V
O
/ VIN; Q
rr
is the reverse
recover charge; t
DL
and t
DT
are leading and trailing edge dead
time, and t
ON
& t
OFF
are the switching intervals.
These equations do not include the gate-charge losses that
are proportional to the total gate charge and the switching
frequency and partially dissipated by the internal gate
resistance of the MOSFETs. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
ISL8118 DC/DC Converter Application Circuit
Detailed information on the application circuit, including a
complete Bill of Materials and circuit board description, can
be found in application note AN1204. See Intersil’s home
page on the web: http://www.intersil.com.
I
IN RMS
K
ICM
I
O
=
I
IN RMS
I
O
2
DD
2

I
2
12
--------
D+=
OR
D
V
O
VIN
----------
=
(EQ. 27)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
K
ICM
DUTY CYCLE (D)
FIGURE 12. INPUT-CAPACITOR CURRENT MULTIPLIER FOR
SINGLE-PHASE BUCK CONVERTER
0.5Io
0.25Io
DI = 0Io
P
BOTTOM
I
O
2
I
2
12
--------
+


r
DS ONB
N
B
--------------------------
1DP
DEAD
+=
(EQ. 28)
P
DEAD
I
O
I
12
------
+


V
DT
t
DT
I
O
I
12
------


V
DB
t
DB
+ F
S
=
(EQ. 29)
P
TOP
I
O
2
I
2
12
--------
+


r
DS ON,T
N
T
---------------------------
DP
SW
P
Qrr
++=
(EQ. 30)
P
SW
I
O
I
12
------
+


t
OFF
I
O
I
12
------


t
ON
+ VIN F
S
=
(EQ. 31)
P
Qrr
Q
rr
VIN F
S
=
(EQ. 32)
ISL8118
20
FN6325.3
August 12, 2014
Submit Document Feedback
ISL8118
Package Outline Drawing
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/07
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
BOTTOM VIEW
SIDE VIEW
5.00
A
5.00
B
INDEX AREA
PIN 1
6
(4X) 0.15
28X 0.55 ± 0.10 4
A
28X 0.25
M0.10 C B
14
8
4X
0.50
24X
3.0
6
PIN #1 INDEX AREA
3 .10 ± 0 . 15
0 . 90 ± 0.1
BASE PLANE
SEE DETAIL "X"
SEATING PLANE
0.10
C
C
0.08 C
0 . 2 REF
C
0 . 05 MAX.
0 . 00 MIN.
5
( 3. 10)
( 4. 65 TYP )
( 24X 0 . 50)
(28X 0 . 25 )
( 28X 0 . 75)
15
22
21
7
1
28
+ 0.05
- 0.07

ISL8118IRZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers 3 3V-20V INPUT SYNC PWM CONT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet