1. General description
The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding
asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to
Q6). The counter advances on the HIGH to LOW transition of CP
. A HIGH on MR clears
all counter stages and forces all outputs LOW, independent of CP
. Each counter stage is a
static toggle flip-flop.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall time
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Frequency dividers
Time delay circuits
4. Ordering information
HEF4024B
7-stage binary counter
Rev. 7 — 18 November 2011 Product data sheet
Table 1. Ordering information
All types operate from
40
C to +85
C
Type number Package
Name Description Version
HEF4024BP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
HEF4024BT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
