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HEF4024BP,652

P1-P3P4-P6P7-P9P10-P12P13-P14
HEF4024B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 18 November 2011 4 of 14
NXP Semiconductors
HEF4024B
7-stage binary counter
8. Limiting values
[1] For DIP14 package: P
tot
derates linearly with 12 mW/K above 70 C.
[2] For SO14 package: P
tot
derates linearly with 8 mW/K above 70 C.
9. Recommended operating conditions
10. Static characteristics
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +18 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
DD
+ 0.5 V - 10 mA
V
I
input voltage 0.5 V
DD
+ 0.5 V
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
DD
+ 0.5 V - 10 mA
I
I/O
input/output current - 10 mA
I
DD
supply current - 50 mA
T
stg
storage temperature 65 +150 C
T
amb
ambient temperature in free air 40 +85 C
P
tot
total power dissipation T
amb
40 C to +85 C
DIP14 package
[1]
- 750 mW
SO14 package
[2]
- 500 mW
P power dissipation per output - 100 mW
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 3 15 V
V
I
input voltage 0 V
DD
V
T
amb
ambient temperature in free air 40 +85 C
t/V input transition rise and fall rate V
DD
= 5 V - 3.75 s/V
V
DD
= 10 V - 0.5 s/V
V
DD
= 15 V - 0.08 s/V
Table 6. Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
; unless otherwise specified.
Symbol Parameter Conditions V
DD
T
amb
= 40 C T
amb
= 25 C T
amb
= 85 C Unit
Min Max Min Max Min Max
V
IH
HIGH-level input voltage I
O
< 1 A 5 V 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
V
IL
LOW-level input voltage I
O
< 1 A5 V-1.5-1.5-1.5V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
HEF4024B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 18 November 2011 5 of 14
NXP Semiconductors
HEF4024B
7-stage binary counter
11. Dynamic characteristics
V
OH
HIGH-level output voltage I
O
< 1 A 5 V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
V
OL
LOW-level output voltage I
O
< 1 A 5 V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
I
OH
HIGH-level output current V
O
= 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA
V
O
= 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA
V
O
= 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA
V
O
= 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA
I
OL
LOW-level output current V
O
= 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA
V
O
= 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
V
O
= 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA
I
I
input leakage current 15 V - 0.3 - 0.3 - 1.0 A
I
DD
supply current I
O
= 0 A 5 V - 20 - 20 - 30 A
10 V - 40 - 40 - 60 A
15 V - 80 - 80 - 120 A
C
I
input capacitance - - - - 7.5 - - pF
Table 6. Static characteristics …continued
V
SS
= 0 V; V
I
= V
SS
or V
DD
; unless otherwise specified.
Symbol Parameter Conditions V
DD
T
amb
= 40 C T
amb
= 25 C T
amb
= 85 C Unit
Min Max Min Max Min Max
Table 7. Dynamic characteristics
V
SS
= 0 V; T
amb
= 25
C; for test circuit see Figure 6; unless otherwise specified.
Symbol Parameter Conditions V
DD
Extrapolation formula
[1]
Min Typ Max Unit
t
PHL
HIGH to LOW
propagation delay
CP ® Q0;
see Figure 5
5 V 73 ns + (0.55 ns/pF)C
L
- 100 200 ns
10 V 29 ns + (0.23 ns/pF)C
L
-4075ns
15 V 17 ns + (0.16 ns/pF)C
L
-2550ns
Qn Qn + 1;
see Figure 5
5 V 33 ns + (0.55 ns/pF)C
L
- 60 120 ns
10 V 14 ns + (0.23 ns/pF)C
L
-2550ns
15 V 12 ns + (0.16 ns/pF)C
L
-2040ns
MR Qn;
see Figure 5
5 V 93 ns + (0.55 ns/pF)C
L
- 120 240 ns
10 V 34 ns + (0.23 ns/pF)C
L
-4590ns
15 V 22 ns + (0.16 ns/pF)C
L
-3060ns
t
PLH
LOW to HIGH
propagation delay
CP ® Q0;
see Figure 5
5 V 78 ns + (0.55 ns/pF)C
L
- 105 210 ns
10 V 34 ns + (0.23 ns/pF)C
L
-4585ns
15 V 22 ns + (0.16 ns/pF)C
L
-3060ns
Qn Qn + 1
see Figure 5
5 V 23 ns + (0.55 ns/pF)C
L
- 50 100 ns
10 V 9 ns + (0.23 ns/pF)C
L
-2040ns
15 V 7 ns + (0.16 ns/pF)C
L
-1530ns
HEF4024B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 18 November 2011 6 of 14
NXP Semiconductors
HEF4024B
7-stage binary counter
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
[2] t
t
is the same as t
TLH
and t
THL
.
t
t
transition time see Figure 5 5 V
[2]
10 ns + (1.00 ns/pF)C
L
- 60 120 ns
10 V 9 ns + (0.42 ns/pF)C
L
-3060ns
15 V 6 ns + (0.28 ns/pF)C
L
-2040ns
t
W
pulse width CP HIGH;
minimum width
see Figure 5
5 V 60 30 - ns
10 V 30 15 - ns
15 V 20 10 - ns
MR HIGH;
minimum width
see Figure 5
5 V 80 40 - ns
10 V 35 20 - ns
15 V 25 15 - ns
t
rec
recovery time MR;
see Figure 5
5 V 20 10 - ns
10 V 15 5 - ns
15 V 15 5 - ns
f
max
maximum
frequency
CP input;
J = K = HIGH;
see Figure 5
5 V 5 10 - MHz
10 V 13 25 - MHz
15 V 18 35 - MHz
Table 7. Dynamic characteristics
…continued
V
SS
= 0 V; T
amb
= 25
C; for test circuit see Figure 6; unless otherwise specified.
Symbol Parameter Conditions V
DD
Extrapolation formula
[1]
Min Typ Max Unit
Table 8. Dynamic power dissipation P
D
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol Parameter V
DD
Typical formula for P
D
(W) Where:
P
D
dynamic power
dissipation
5 V P
D
= 500 f
i
+ (f
o
C
L
) V
DD
2
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
DD
= supply voltage in V;
(f
o
C
L
) = sum of the outputs.
10 V P
D
= 2100 f
i
+ (f
o
C
L
) V
DD
2
15 V P
D
= 5200 f
i
+ (f
o
C
L
) V
DD
2
P1-P3P4-P6P7-P9P10-P12P13-P14

HEF4024BP,652

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Manufacturer:
NXP Semiconductors
Description:
Counter ICs 7-STAGE BIN COUNTER
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