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HEF4024BP,652
P1-P3
P4-P6
P7-P9
P10-P12
P13-P14
HEF4024B
All informatio
n provided in this d
ocument is subje
ct to legal disclaimer
s.
© NXP B.V
. 201
1. All rights reserved.
Product data sheet
Rev
. 7
— 18 November 201
1
7 of 14
NXP Semiconductors
HEF4024B
7-st
age binary counter
12. W
aveforms
V
OH
and V
OL
are typical output voltages levels that occur with the output load.
Measurement points are given in
T
able 9
.
Fig 5.
Waveforms showing pr
opagation delays for MR to Qn and CP
to Q0, minimum
MR and CP
pulse wid
ths
and recovery time for MR.
MR input
CP input
Q0 or Qn
output
t
W
t
PHL
1/f
max
t
rec
V
M
V
M
001aab910
t
PLH
t
W
t
TLH
t
THL
t
PHL
V
M
T
able 9.
Mea
surement point
s
Supply volt
age
Input
Output
V
DD
V
M
V
M
5 V to 15 V
0.5V
DD
0.5V
DD
HEF4024B
All informatio
n provided in this d
ocument is subje
ct to legal disclaimer
s.
© NXP B.V
. 2011. All rights reserved.
Product data sheet
Rev
. 7
— 18 November 201
1
8 of 14
NXP Semiconductors
HEF4024B
7-st
age binary counter
a.
Input waveforms
b.
T
est circuit
T
est data is given in
T
able 10
.
Definitions for test circuit:
DUT = Device Under T
est.
C
L
= load capacitance including jig and probe capacitance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator
.
Fig 6.
T
est circuit
for measuring switching
times
V
M
V
M
t
W
t
W
10 %
90 %
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
90 %
10 %
t
f
t
r
t
r
t
f
001aaj781
V
DD
V
I
V
O
001aag182
DUT
C
L
R
T
G
T
able 10.
T
est da
t
a
Supply volt
age
Input
Load
V
DD
V
I
t
r
, t
f
C
L
5 V to 15 V
V
SS
or V
DD
20 ns
50 pF
HEF4024B
All informatio
n provided in this d
ocument is subje
ct to legal disclaimer
s.
© NXP B.V
. 2011. All rights reserved.
Product data sheet
Rev
. 7
— 18 November 201
1
9 of 14
NXP Semiconductors
HEF4024B
7-st
age binary counter
13. Package
outline
Fig 7.
Pac
kage outline SOT27-1
(DIP14)
UNIT
A
max.
1
2
(1)
(1)
b
1
cD
(1)
Z
Ee
M
H
L
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT27-1
99-12-27
03-02-13
A
min.
A
max.
b
max.
w
M
E
e
1
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
0.254
2.54
7.62
8.25
7.80
10.0
8.3
2.2
4.2
0.51
3.2
0.068
0.044
0.021
0.015
0.77
0.73
0.014
0.009
0.26
0.24
0.14
0.12
0.01
0.1
0.3
0.32
0.31
0.39
0.33
0.087
0.17
0.02
0.13
050G04
MO-001
SC-501-14
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w
M
b
1
e
D
A
2
Z
14
1
8
7
b
E
pin 1 index
0
5
10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
P1-P3
P4-P6
P7-P9
P10-P12
P13-P14
HEF4024BP,652
Mfr. #:
Buy HEF4024BP,652
Manufacturer:
NXP Semiconductors
Description:
Counter ICs 7-STAGE BIN COUNTER
Lifecycle:
New from this manufacturer.
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