DATASHEET
4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
9FGV0431
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR 1
9FGV0431 OCTOBER 18, 2016
Description
The 9FGV0431 is a 4-output very low power clock
generator for PCIe Gen 1, 2 and 3 applications. The device
has 4 output enables for clock management and supports 2
different spread spectrum levels in addition to spread off.
Recommended Application
PCIe Gen1-2-3 Clock Generator
Output Features
4 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF
pairs
1 - 1.8V LVCMOS REF output w/Wake-On-Lan
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 1.5ps RMS
Features/Benefits
1.8V operation; reduced power consuption
OE# pins; support DIF power management
LP-HCSL differential clock outputs; reduced power and
board space
Programmable Slew rate for each output; allows tuning
for various line lengths
Programmable output amplitude; allows tuning for
various application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy
controllers
Space saving 32-pin 5x5 mm MLF; minimal board space
Selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Block Diagram
X1_25
X2
DIF(3:0)
CONTROL
LOGIC
SS_EN_tri
CKPWRGD_PD#
SDATA_3.3
SS Capable PLL
4
OSC
R
E
F
1
.
8
OE(3:0)#
SCLK_3.3
SADR
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR 2
9FGV0431 OCTOBER 18, 2016
Pin Configuration
SMBus Address Selection Table
Power Management Table
Power Connections
vSS_EN_tri
^CKPWRGD_PD#
GND
vOE3#
DIF3#
DIF3
GND
VDDO1.8
32 31 30 29 28 27 26 25
GNDXTAL 1
24
vOE2#
XIN/CLKIN_25 2
23
DIF2#
X2 3
22
DIF2
VDDXTAL1.8 4
21
VDDA1.8
VDDREF1.8 5
20
GNDA
vSADR/REF1.8 6
19
DIF1#
GNDREF
7
18
DIF1
GNDDIG
817vOE1#
9 10111213141516
VDDDIG1.8
SCLK_3.3
SDATA_3.3
vOE0#
DIF0
DIF0#
GND
VDDO1.8
32-pin MLF, 5x5 mm, 0.5mm pitch
v prefix indicates internal 120KOhm pull down resistor
9FGV0431
^ prefix indicates internal 120KOhm pull up resisto
r
SADR Address
0 1101000
1 1101010
+ Read/Write Bit
x
x
State of SADR on first application
of CKPWRGD_PD#
OEx# True O/P Comp. O/P
0XXLowLow
Hi-Z
1
1 1 0 Running Running Running
1 0 1 Low Low Low
REF
CKPWRGD_PD#
SMBus
OE bit
DIFx
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is Low.
Pin Number
VDD GND
41
57
98, 30
16, 25 15, 26
21 20 PLL Analog
REF Output
Description
XTAL Analo
g
Di
ital Power
DIF outputs
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR 3
9FGV0431 OCTOBER 18, 2016
Pin Descriptions
Pin# Pin Name Type Pin Description
1 GNDXTAL GND GND for XTAL
2 XIN/CLKIN_25 IN Crystal input or Reference Clock input. Nominally 25MHz.
3 X2 OUT Crystal output.
4 VDDXTAL1.8 PWR Power supply for XTAL, nominal 1.8V
5 VDDREF1.8 PWR VDD for REF output. nominal 1.8V.
6 vSADR/REF1.8
LATCHED
I/O
Latch to select SMBus Address/1.8V LVCMOS copy of X1 pin.
7 GNDREF GND Ground pin for the REF outputs.
8 GNDDIG GND Ground pin for digital circuitry
9 VDDDIG1.8 PWR 1.8V digital power (dirty power)
10 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant.
11 SDATA_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant.
12 vOE0# IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
13 DIF0 OUT Differential true clock output
14 DIF0# OUT Differential Complementary clock output
15 GND GND Ground pin.
16 VDDO1.8 PWR Power supply for outputs, nominally 1.8V.
17 vOE1# IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
18 DIF1 OUT Differential true clock output
19 DIF1# OUT Differential Complementary clock output
20 GNDA GND Ground pin for the PLL core.
21 VDDA1.8 PWR 1.8V power for the PLL core.
22 DIF2 OUT Differential true clock output
23 DIF2# OUT Differential Complementary clock output
24 vOE2# IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
25 VDDO1.8 PWR Power supply for outputs, nominally 1.8V.
26 GND GND Ground pin.
27 DIF3 OUT Differential true clock output
28 DIF3# OUT Differential Complementary clock output
29 vOE3# IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
30 GND GND Ground pin.
31 ^CKPWRGD_PD# IN
Input notifies device to sample latched inputs and start up on first high assertion.
Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
32 vSS_EN_tri LATCHED IN
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off

9FGV0431AKLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products PCIe CLOCK GENERATOR GEN 1/2/3, 4 OUT
Lifecycle:
New from this manufacturer.
Delivery:
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