9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR 5
9FGV0431 OCTOBER 18, 2016
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGV0431. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics–Current Consumption
Electrical Characteristics–Output Duty Cycle, Jitter, and Skew Characterisitics
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
1.8V Supply Voltage VDDx1.8 Applies to All VDD pins -0.5 2.5 V 1,2
Input Voltage V
IN
DD
+0.3V V 1, 3
Input High Voltage, SMBus V
IHSMB
SMBus clock and data pins 3.6V V 1
Storage Temperature Ts -65 150 °C
1
Junction Temperature Tj 125 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
DDAOP
VDDA, All outputs active @100MHz
68
mA 1
I
DDOP
VDD, All outputs active @100MHz
26 30
mA 1
Suspend Supply Current
I
DDSUSP
VDDxxx, PD# = 0, Wake-On-LAN enabled
68
mA 1
Powerdown Current
I
DDPD
PD#=0 0.6 1 mA
1, 2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Assuming REF is not running in power down state
Operating Supply Current
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Duty Cycle t
DC
Measured differentially, PLL Mode 45 50.1 55 % 1
Skew, Output to Output t
sk3
T
= 50% 37 50 ps 1
Jitter, Cycle to cycle t
jcyc-cyc
PLL mode 12 50 ps 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform